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move the driver into shared 'files' directory and rename all symbols
from mediatek/mtk to ralink.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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At this moment mt7620 ethernet driver doesn't support rgmii delays
configuration. SoC MT7620 have bits 2 and 3 in GPC1 an GPC2 to configure
delays for rx and tx rgmii interface.
This patch adds rx/tx rgmii delay configuration from dts.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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The port initialisation is based on assumption that phy address and
port number is the same. SoC allow different numbers and some board
have it.
Use phy address instead the port number to make sure that correct
addresses are polled.
In situation when only one PHY with address 0x0 is conected to
port 4, autopolling is broken.
This patch make autopolling correct when port number and phy address
are different.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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The phy handling code forces a phy mdio address and the switch port to
which a phy is attached to be the same. Albeit such a configuration is
used for most boards, it isn't for all.
Pass the switch port number to the ethernet phy connect functions, to
ensure the correct list entry is edited and not the list entry that
matches th phys mdio address.
Use the mdio address with mdiobus_get_phy instead of the port number,
to make sure the expected ethernet phy gets connected.
Signed-off-by: Mathias Kresin <dev@kresin.me>
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Preparation for sharing offload code with the mediatek target through
generic files/
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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