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move the driver into shared 'files' directory and rename all symbols
from mediatek/mtk to ralink.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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The phy handling code forces a phy mdio address and the switch port to
which a phy is attached to be the same. Albeit such a configuration is
used for most boards, it isn't for all.
Pass the switch port number to the ethernet phy connect functions, to
ensure the correct list entry is edited and not the list entry that
matches th phys mdio address.
Use the mdio address with mdiobus_get_phy instead of the port number,
to make sure the expected ethernet phy gets connected.
Signed-off-by: Mathias Kresin <dev@kresin.me>
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The whole logic in fe_phy_connect() is based on the asumption that mdio
address and switch port id are equal. Albeit it is true for most
boards, it doesn't is for all.
It isn't yet clear which subtargets/boards require the devicetree less
ethernet phy handling. Hence change the code in a way that it doesn't
touch ethernet phys which were early attached and are already handled.
Signed-off-by: Mathias Kresin <dev@kresin.me>
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When PHY's are defined on the MDIO bus in the DTS, gigabit support was
being masked out for no apparent reason, pegging all such ports to 10/100.
If gigabit support must be disabled for some reason, there should be a
"max-speed" property in the DTS.
Reported-by: James McKenzie <openwrt@madingley.org>
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
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Preparation for sharing offload code with the mediatek target through
generic files/
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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