diff options
Diffstat (limited to 'source/distorm')
| -rw-r--r-- | source/distorm/config.h | 168 | ||||
| -rw-r--r-- | source/distorm/decoder.c | 651 | ||||
| -rw-r--r-- | source/distorm/decoder.h | 33 | ||||
| -rw-r--r-- | source/distorm/distorm.c | 409 | ||||
| -rw-r--r-- | source/distorm/instructions.c | 598 | ||||
| -rw-r--r-- | source/distorm/instructions.h | 463 | ||||
| -rw-r--r-- | source/distorm/insts.c | 7939 | ||||
| -rw-r--r-- | source/distorm/insts.h | 64 | ||||
| -rw-r--r-- | source/distorm/mnemonics.c | 284 | ||||
| -rw-r--r-- | source/distorm/operands.c | 1291 | ||||
| -rw-r--r-- | source/distorm/operands.h | 28 | ||||
| -rw-r--r-- | source/distorm/prefix.c | 368 | ||||
| -rw-r--r-- | source/distorm/prefix.h | 64 | ||||
| -rw-r--r-- | source/distorm/textdefs.c | 173 | ||||
| -rw-r--r-- | source/distorm/textdefs.h | 57 | ||||
| -rw-r--r-- | source/distorm/wstring.c | 48 | ||||
| -rw-r--r-- | source/distorm/wstring.h | 35 | ||||
| -rw-r--r-- | source/distorm/x86defs.h | 82 |
18 files changed, 12755 insertions, 0 deletions
diff --git a/source/distorm/config.h b/source/distorm/config.h new file mode 100644 index 0000000..805a7d6 --- /dev/null +++ b/source/distorm/config.h @@ -0,0 +1,168 @@ +/* +config.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef CONFIG_H +#define CONFIG_H + +#include "distorm/distorm.h" + + +/* diStorm version number. */ +#define __DISTORMV__ 0x030304 + + +/* + * 64 bit offsets support: + * This macro should be defined from compiler command line flags, e.g: -DSUPPORT_64BIT_OFFSET + * Note: make sure that the caller (library user) defines it too! + */ +/* #define SUPPORT_64BIT_OFFSET */ + +/* + * If you compile diStorm as a dynamic library (.dll or .so) file, make sure you uncomment the next line. + * So the interface functions will be exported, otherwise they are useable only for static library. + * For example, this macro is being set for compiling diStorm as a .dll for Python with CTypes. + */ +/* #define DISTORM_DYNAMIC */ + +/* + * If DISTORM_LIGHT is defined, everything involved in formatting the instructions + * as text will be excluded from compilation. + * distorm_decode(..) and distorm_format(..) will not be available. + * This will decrease the size of the executable and leave you with decomposition functionality only. + * + * Note: it should be either set in the preprocessor definitions manually or in command line -D switch. + * #define DISTORM_LIGHT + */ + +/* + * diStorm now supports little/big endian CPU's. + * It should detect the endianness according to predefined macro's of the compiler. + * If you don't use GCC/MSVC you will have to define it on your own. + */ + +/* These macros are used in order to make the code portable. */ +#ifdef __GNUC__ + +#include <stdint.h> + +#define _DLLEXPORT_ +#define _FASTCALL_ +#define _INLINE_ static +/* GCC ignores this directive... */ +/*#define _FASTCALL_ __attribute__((__fastcall__))*/ + +/* Set endianity (supposed to be LE though): */ +#ifdef __BIG_ENDIAN__ + #define BE_SYSTEM +#endif + +/* End of __GCC__ */ + +#elif __WATCOMC__ + +#include <stdint.h> + +#define _DLLEXPORT_ +#define _FASTCALL_ +#define _INLINE_ __inline + +/* End of __WATCOMC__ */ + +#elif __DMC__ + +#include <stdint.h> + +#define _DLLEXPORT_ +#define _FASTCALL_ +#define _INLINE_ __inline + +/* End of __DMC__ */ + +#elif __TINYC__ + +#include <stdint.h> + +#define _DLLEXPORT_ +#define _FASTCALL_ +#define _INLINE_ + +/* End of __TINYC__ */ + +#elif _MSC_VER + +/* stdint alternative is defined in distorm.h */ + +#define _DLLEXPORT_ __declspec(dllexport) +#define _FASTCALL_ __fastcall +#define _INLINE_ __inline + +/* Set endianity (supposed to be LE though): */ +#if !defined(_M_IX86) && !defined(_M_X64) + #define BE_SYSTEM +#endif + +#endif /* #elif _MSC_VER */ + +/* If the library isn't compiled as a dynamic library don't export any functions. */ +#ifndef DISTORM_DYNAMIC +#undef _DLLEXPORT_ +#define _DLLEXPORT_ +#endif + +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + +/* Define stream read functions for big endian systems. */ +#ifdef BE_SYSTEM +/* + * These functions can read from the stream safely! + * Swap endianity of input to little endian. + */ +static _INLINE_ int16_t RSHORT(const uint8_t *s) +{ + return s[0] | (s[1] << 8); +} +static _INLINE_ uint16_t RUSHORT(const uint8_t *s) +{ + return s[0] | (s[1] << 8); +} +static _INLINE_ int32_t RLONG(const uint8_t *s) +{ + return s[0] | (s[1] << 8) | (s[2] << 16) | (s[3] << 24); +} +static _INLINE_ uint32_t RULONG(const uint8_t *s) +{ + return s[0] | (s[1] << 8) | (s[2] << 16) | (s[3] << 24); +} +static _INLINE_ int64_t RLLONG(const uint8_t *s) +{ + return s[0] | (s[1] << 8) | (s[2] << 16) | (s[3] << 24) | ((uint64_t)s[4] << 32) | ((uint64_t)s[5] << 40) | ((uint64_t)s[6] << 48) | ((uint64_t)s[7] << 56); +} +static _INLINE_ uint64_t RULLONG(const uint8_t *s) +{ + return s[0] | (s[1] << 8) | (s[2] << 16) | (s[3] << 24) | ((uint64_t)s[4] << 32) | ((uint64_t)s[5] << 40) | ((uint64_t)s[6] << 48) | ((uint64_t)s[7] << 56); +} +#else +/* Little endian macro's will just make the cast. */ +#define RSHORT(x) *(int16_t *)x +#define RUSHORT(x) *(uint16_t *)x +#define RLONG(x) *(int32_t *)x +#define RULONG(x) *(uint32_t *)x +#define RLLONG(x) *(int64_t *)x +#define RULLONG(x) *(uint64_t *)x +#endif + +#endif /* CONFIG_H */ diff --git a/source/distorm/decoder.c b/source/distorm/decoder.c new file mode 100644 index 0000000..a54e5b5 --- /dev/null +++ b/source/distorm/decoder.c @@ -0,0 +1,651 @@ +/* +decoder.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "decoder.h" +#include "instructions.h" +#include "insts.h" +#include "prefix.h" +#include "x86defs.h" +#include "operands.h" +#include "insts.h" +#include "distorm/mnemonics.h" +#include "compat.h" + + +/* Instruction Prefixes - Opcode - ModR/M - SIB - Displacement - Immediate */ + +static _DecodeType decode_get_effective_addr_size(_DecodeType dt, _iflags decodedPrefixes) +{ + /* + * This table is to map from the current decoding mode to an effective address size: + * Decode16 -> Decode32 + * Decode32 -> Decode16 + * Decode64 -> Decode32 + */ + static volatile _DecodeType AddrSizeTable[] = {Decode32Bits, Decode16Bits, Decode32Bits}; + + /* Switch to non default mode if prefix exists, only for ADDRESS SIZE. */ + if (decodedPrefixes & INST_PRE_ADDR_SIZE) dt = AddrSizeTable[dt]; + return dt; +} + +static _DecodeType decode_get_effective_op_size(_DecodeType dt, _iflags decodedPrefixes, unsigned int rex, _iflags instFlags) +{ + /* + * This table is to map from the current decoding mode to an effective operand size: + * Decode16 -> Decode32 + * Decode32 -> Decode16 + * Decode64 -> Decode16 + * Not that in 64bits it's a bit more complicated, because of REX and promoted instructions. + */ + static volatile _DecodeType OpSizeTable[] = {Decode32Bits, Decode16Bits, Decode16Bits}; + + if (decodedPrefixes & INST_PRE_OP_SIZE) return OpSizeTable[dt]; + + if (dt == Decode64Bits) { + /* + * REX Prefix toggles data size to 64 bits. + * Operand size prefix toggles data size to 16. + * Default data size is 32 bits. + * Promoted instructions are 64 bits if they don't require a REX perfix. + * Non promoted instructions are 64 bits if the REX prefix exists. + */ + /* Automatically promoted instructions have only INST_64BITS SET! */ + if (((instFlags & (INST_64BITS | INST_PRE_REX)) == INST_64BITS) || + /* Other instructions in 64 bits can be promoted only with a REX prefix. */ + ((decodedPrefixes & INST_PRE_REX) && (rex & PREFIX_EX_W))) dt = Decode64Bits; + else dt = Decode32Bits; /* Default. */ + } + return dt; +} + +/* A helper macro to convert from diStorm's CPU flags to EFLAGS. */ +#define CONVERT_FLAGS_TO_EFLAGS(dst, src, field) dst->field = ((src->field & D_COMPACT_SAME_FLAGS) | \ + ((src->field & D_COMPACT_IF) ? D_IF : 0) | \ + ((src->field & D_COMPACT_DF) ? D_DF : 0) | \ + ((src->field & D_COMPACT_OF) ? D_OF : 0)); + +static _DecodeResult decode_inst(_CodeInfo* ci, _PrefixState* ps, _DInst* di) +{ + /* Remember whether the instruction is privileged. */ + uint16_t privilegedFlag = 0; + + /* The ModR/M byte of the current instruction. */ + unsigned int modrm = 0; + + /* The REX/VEX prefix byte value. */ + unsigned int vrex = ps->vrex; + + /* + * Backup original input, so we can use it later if a problem occurs + * (like not enough data for decoding, invalid opcode, etc). + */ + const uint8_t* startCode = ci->code; + + /* Holds the info about the current found instruction. */ + _InstInfo* ii = NULL; + _InstInfo iip; /* Privileged instruction cache. */ + _InstSharedInfo* isi = NULL; + + /* Used only for special CMP instructions which have pseudo opcodes suffix. */ + unsigned char cmpType = 0; + + /* + * Indicates whether it is right to LOCK the instruction by decoding its first operand. + * Only then you know if it's ok to output the LOCK prefix's text... + * Used for first operand only. + */ + int lockable = FALSE; + + /* Calculate (and cache) effective-operand-size and effective-address-size only once. */ + _DecodeType effOpSz, effAdrSz; + _iflags instFlags; + + ii = inst_lookup(ci, ps); + if (ii == NULL) goto _Undecodable; + isi = &InstSharedInfoTable[ii->sharedIndex]; + instFlags = FlagsTable[isi->flagsIndex]; + privilegedFlag = ii->opcodeId & OPCODE_ID_PRIVILEGED; + + if (privilegedFlag) { + /* + * Copy the privileged instruction info so we can remove the privileged bit + * from the opcodeId field. This makes sure we're not modifying the tables + * in case we lookup this privileged instruction later. + */ + iip = *ii; + iip.opcodeId &= ~OPCODE_ID_PRIVILEGED; + ii = &iip; + } + + /* + * If both REX and OpSize are available we will have to disable the OpSize, because REX has precedence. + * However, only if REX.W is set ! + * We had to wait with this test, since the operand size may be a mandatory prefix, + * and we know it only after prefetching. + */ + if ((ps->prefixExtType == PET_REX) && + (ps->decodedPrefixes & INST_PRE_OP_SIZE) && + (!ps->isOpSizeMandatory) && + (vrex & PREFIX_EX_W)) { + ps->decodedPrefixes &= ~INST_PRE_OP_SIZE; + prefixes_ignore(ps, PFXIDX_OP_SIZE); + } + + /* + * In this point we know the instruction we are about to decode and its operands (unless, it's an invalid one!), + * so it makes it the right time for decoding-type suitability testing. + * Which practically means, don't allow 32 bits instructions in 16 bits decoding mode, but do allow + * 16 bits instructions in 32 bits decoding mode, of course... + + * NOTE: Make sure the instruction set for 32 bits has explicitly this specific flag set. + * NOTE2: Make sure the instruction set for 64 bits has explicitly this specific flag set. + + * If this is the case, drop what we've got and restart all over after DB'ing that byte. + + * Though, don't drop an instruction which is also supported in 16 and 32 bits. + */ + + /* ! ! ! DISABLED UNTIL FURTHER NOTICE ! ! ! Decode16Bits CAN NOW DECODE 32 BITS INSTRUCTIONS ! ! !*/ + /* if (ii && (dt == Decode16Bits) && (instFlags & INST_32BITS) && (~instFlags & INST_16BITS)) ii = NULL; */ + + /* Drop instructions which are invalid in 64 bits. */ + if ((ci->dt == Decode64Bits) && (instFlags & INST_INVALID_64BITS)) goto _Undecodable; + + /* If it's only a 64 bits instruction drop it in other decoding modes. */ + if ((ci->dt != Decode64Bits) && (instFlags & INST_64BITS_FETCH)) goto _Undecodable; + + if (instFlags & INST_MODRM_REQUIRED) { + /* If the ModRM byte is not part of the opcode, skip the last byte code, so code points now to ModRM. */ + if (~instFlags & INST_MODRM_INCLUDED) { + ci->code++; + if (--ci->codeLen < 0) goto _Undecodable; + } + modrm = *ci->code; + + /* Some instructions enforce that reg=000, so validate that. (Specifically EXTRQ). */ + if ((instFlags & INST_FORCE_REG0) && (((modrm >> 3) & 7) != 0)) goto _Undecodable; + /* Some instructions enforce that mod=11, so validate that. */ + if ((instFlags & INST_MODRR_REQUIRED) && (modrm < INST_DIVIDED_MODRM)) goto _Undecodable; + } + + ci->code++; /* Skip the last byte we just read (either last opcode's byte code or a ModRM). */ + + /* Cache the effective operand-size and address-size. */ + effOpSz = decode_get_effective_op_size(ci->dt, ps->decodedPrefixes, vrex, instFlags); + effAdrSz = decode_get_effective_addr_size(ci->dt, ps->decodedPrefixes); + + COMPAT(memset)(di, 0, sizeof(_DInst)); + di->base = R_NONE; + + /* + * Try to extract the next operand only if the latter exists. + * For example, if there is not first operand, no reason to try to extract second operand... + * I decided that a for-break is better for readability in this specific case than goto. + * Note: do-while with a constant 0 makes the compiler warning about it. + */ + for (;;) { + if (isi->d != OT_NONE) { + if (!operands_extract(ci, di, ii, instFlags, (_OpType)isi->d, ONT_1, modrm, ps, effOpSz, effAdrSz, &lockable)) goto _Undecodable; + } else break; + + if (isi->s != OT_NONE) { + if (!operands_extract(ci, di, ii, instFlags, (_OpType)isi->s, ONT_2, modrm, ps, effOpSz, effAdrSz, NULL)) goto _Undecodable; + } else break; + + /* Use third operand, only if the flags says this InstInfo requires it. */ + if (instFlags & INST_USE_OP3) { + if (!operands_extract(ci, di, ii, instFlags, (_OpType)((_InstInfoEx*)ii)->op3, ONT_3, modrm, ps, effOpSz, effAdrSz, NULL)) goto _Undecodable; + } else break; + + /* Support for a fourth operand is added for (i.e:) INSERTQ instruction. */ + if (instFlags & INST_USE_OP4) { + if (!operands_extract(ci, di, ii, instFlags, (_OpType)((_InstInfoEx*)ii)->op4, ONT_4, modrm, ps, effOpSz, effAdrSz, NULL)) goto _Undecodable; + } + break; + } /* Continue here after all operands were extracted. */ + + /* If it were a 3DNow! instruction, we will have to find the instruction itself now that we got its operands extracted. */ + if (instFlags & INST_3DNOW_FETCH) { + ii = inst_lookup_3dnow(ci); + if (ii == NULL) goto _Undecodable; + isi = &InstSharedInfoTable[ii->sharedIndex]; + instFlags = FlagsTable[isi->flagsIndex]; + } + + /* Check whether pseudo opcode is needed, only for CMP instructions: */ + if (instFlags & INST_PSEUDO_OPCODE) { + if (--ci->codeLen < 0) goto _Undecodable; + cmpType = *ci->code; + ci->code++; + if (instFlags & INST_PRE_VEX) { + /* AVX Comparison type must be between 0 to 32, otherwise Reserved. */ + if (cmpType >= INST_VCMP_MAX_RANGE) goto _Undecodable; + } else { + /* SSE Comparison type must be between 0 to 8, otherwise Reserved. */ + if (cmpType >= INST_CMP_MAX_RANGE) goto _Undecodable; + } + } + + /* + * There's a limit of 15 bytes on instruction length. The only way to violate + * this limit is by putting redundant prefixes before an instruction. + * start points to first prefix if any, otherwise it points to instruction first byte. + */ + if ((ci->code - ps->start) > INST_MAXIMUM_SIZE) goto _Undecodable; /* Drop instruction. */ + + /* + * If we reached here the instruction was fully decoded, we located the instruction in the DB and extracted operands. + * Use the correct mnemonic according to the DT. + * If we are in 32 bits decoding mode it doesn't necessarily mean we will choose mnemonic2, alas, + * it means that if there is a mnemonic2, it will be used. + */ + + /* Start with prefix LOCK. */ + if ((lockable == TRUE) && (instFlags & INST_PRE_LOCK)) { + ps->usedPrefixes |= INST_PRE_LOCK; + di->flags |= FLAG_LOCK; + } else if ((instFlags & INST_PRE_REPNZ) && (ps->decodedPrefixes & INST_PRE_REPNZ)) { + ps->usedPrefixes |= INST_PRE_REPNZ; + di->flags |= FLAG_REPNZ; + } else if ((instFlags & INST_PRE_REP) && (ps->decodedPrefixes & INST_PRE_REP)) { + ps->usedPrefixes |= INST_PRE_REP; + di->flags |= FLAG_REP; + } + + /* If it's JeCXZ the ADDR_SIZE prefix affects them. */ + if ((instFlags & (INST_PRE_ADDR_SIZE | INST_USE_EXMNEMONIC)) == (INST_PRE_ADDR_SIZE | INST_USE_EXMNEMONIC)) { + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + if (effAdrSz == Decode16Bits) di->opcode = ii->opcodeId; + else if (effAdrSz == Decode32Bits) di->opcode = ((_InstInfoEx*)ii)->opcodeId2; + /* Ignore REX.W in 64bits, JECXZ is promoted. */ + else /* Decode64Bits */ di->opcode = ((_InstInfoEx*)ii)->opcodeId3; + } + + /* LOOPxx instructions are also native instruction, but they are special case ones, ADDR_SIZE prefix affects them. */ + else if ((instFlags & (INST_PRE_ADDR_SIZE | INST_NATIVE)) == (INST_PRE_ADDR_SIZE | INST_NATIVE)) { + di->opcode = ii->opcodeId; + + /* If LOOPxx gets here from 64bits, it must be Decode32Bits because Address Size prefix is set. */ + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + } + /* + * Note: + * If the instruction is prefixed by operand size we will format it in the non-default decoding mode! + * So there might be a situation that an instruction of 32 bit gets formatted in 16 bits decoding mode. + * Both ways should end up with a correct and expected formatting of the text. + */ + else if (effOpSz == Decode16Bits) { /* Decode16Bits */ + + /* Set operand size. */ + FLAG_SET_OPSIZE(di, Decode16Bits); + + /* + * If it's a special instruction which has two mnemonics, then use the 16 bits one + update usedPrefixes. + * Note: use 16 bits mnemonic if that instruction supports 32 bit or 64 bit explicitly. + */ + if ((instFlags & INST_USE_EXMNEMONIC) && ((instFlags & (INST_32BITS | INST_64BITS)) == 0)) ps->usedPrefixes |= INST_PRE_OP_SIZE; + di->opcode = ii->opcodeId; + } else if (effOpSz == Decode32Bits) { /* Decode32Bits */ + + /* Set operand size. */ + FLAG_SET_OPSIZE(di, Decode32Bits); + + /* Give a chance for special mnemonic instruction in 32 bits decoding. */ + if (instFlags & INST_USE_EXMNEMONIC) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* Is it a special instruction which has another mnemonic for mod=11 ? */ + if (instFlags & INST_MNEMONIC_MODRM_BASED) { + if (modrm >= INST_DIVIDED_MODRM) di->opcode = ii->opcodeId; + else di->opcode = ((_InstInfoEx*)ii)->opcodeId2; + } else di->opcode = ((_InstInfoEx*)ii)->opcodeId2; + } else di->opcode = ii->opcodeId; + } else { /* Decode64Bits, note that some instructions might be decoded in Decode32Bits above. */ + + /* Set operand size. */ + FLAG_SET_OPSIZE(di, Decode64Bits); + + if (instFlags & (INST_USE_EXMNEMONIC | INST_USE_EXMNEMONIC2)) { + /* + * We shouldn't be here for MODRM based mnemonics with a MOD=11, + * because they must not use REX (otherwise it will get to the wrong instruction which share same opcode). + * See XRSTOR and XSAVEOPT. + */ + if ((instFlags & INST_MNEMONIC_MODRM_BASED) && (modrm >= INST_DIVIDED_MODRM)) goto _Undecodable; + + /* Use third mnemonic, for 64 bits. */ + if ((instFlags & INST_USE_EXMNEMONIC2) && (vrex & PREFIX_EX_W)) { + ps->usedPrefixes |= INST_PRE_REX; + di->opcode = ((_InstInfoEx*)ii)->opcodeId3; + } else di->opcode = ((_InstInfoEx*)ii)->opcodeId2; /* Use second mnemonic. */ + } else di->opcode = ii->opcodeId; + } + + /* If it's a native instruction use OpSize Prefix. */ + if ((instFlags & INST_NATIVE) && (ps->decodedPrefixes & INST_PRE_OP_SIZE)) ps->usedPrefixes |= INST_PRE_OP_SIZE; + + /* Check VEX mnemonics: */ + if ((instFlags & INST_PRE_VEX) && + (((((_InstInfoEx*)ii)->flagsEx & INST_MNEMONIC_VEXW_BASED) && (vrex & PREFIX_EX_W)) || + ((((_InstInfoEx*)ii)->flagsEx & INST_MNEMONIC_VEXL_BASED) && (vrex & PREFIX_EX_L)))) { + di->opcode = ((_InstInfoEx*)ii)->opcodeId2; + } + + /* Or is it a special CMP instruction which needs a pseudo opcode suffix ? */ + if (instFlags & INST_PSEUDO_OPCODE) { + /* + * The opcodeId is the offset to the FIRST pseudo compare mnemonic, + * we will have to fix it so it offsets into the corrected mnemonic. + * Therefore, we use another table to fix the offset. + */ + if (instFlags & INST_PRE_VEX) { + /* Use the AVX pseudo compare mnemonics table. */ + di->opcode = ii->opcodeId + VCmpMnemonicOffsets[cmpType]; + } else { + /* Use the SSE pseudo compare mnemonics table. */ + di->opcode = ii->opcodeId + CmpMnemonicOffsets[cmpType]; + } + } + + /* + * Store the address size inside the flags. + * This is necessary for the caller to know the size of rSP when using PUSHA for example. + */ + FLAG_SET_ADDRSIZE(di, effAdrSz); + + /* Copy DST_WR flag. */ + if (instFlags & INST_DST_WR) di->flags |= FLAG_DST_WR; + + /* Set the unused prefixes mask. */ + di->unusedPrefixesMask = prefixes_set_unused_mask(ps); + + /* Fix privileged. Assumes the privilegedFlag is 0x8000 only. */ + di->flags |= privilegedFlag; + + /* Copy instruction meta. */ + di->meta = isi->meta; + if (di->segment == 0) di->segment = R_NONE; + + /* Take into account the O_MEM base register for the mask. */ + if (di->base != R_NONE) di->usedRegistersMask |= _REGISTERTORCLASS[di->base]; + + /* Copy CPU affected flags. */ + CONVERT_FLAGS_TO_EFLAGS(di, isi, modifiedFlagsMask); + CONVERT_FLAGS_TO_EFLAGS(di, isi, testedFlagsMask); + CONVERT_FLAGS_TO_EFLAGS(di, isi, undefinedFlagsMask); + + /* Calculate the size of the instruction we've just decoded. */ + di->size = (uint8_t)((ci->code - startCode) & 0xff); + return DECRES_SUCCESS; + +_Undecodable: /* If the instruction couldn't be decoded for some reason, drop the first byte. */ + COMPAT(memset)(di, 0, sizeof(_DInst)); + di->base = R_NONE; + + di->size = 1; + /* Clean prefixes just in case... */ + ps->usedPrefixes = 0; + + /* Special case for WAIT instruction: If it's dropped, you have to return a valid instruction! */ + if (*startCode == INST_WAIT_INDEX) { + di->opcode = I_WAIT; + META_SET_ISC(di, ISC_INTEGER); + return DECRES_SUCCESS; + } + + /* Mark that we didn't manage to decode the instruction well, caller will drop it. */ + return DECRES_INPUTERR; +} + +/* + * decode_internal + * + * supportOldIntr - Since now we work with new structure instead of the old _DecodedInst, we are still interested in backward compatibility. + * So although, the array is now of type _DInst, we want to read it in jumps of the old array element's size. + * This is in order to save memory allocation for conversion between the new and the old structures. + * It really means we can do the conversion in-place now. + */ +_DecodeResult decode_internal(_CodeInfo* _ci, int supportOldIntr, _DInst result[], unsigned int maxResultCount, unsigned int* usedInstructionsCount) +{ + _PrefixState ps; + unsigned int prefixSize; + _CodeInfo ci; + unsigned int features; + unsigned int mfc; + + _OffsetType codeOffset = _ci->codeOffset; + const uint8_t* code = _ci->code; + int codeLen = _ci->codeLen; + + /* + * This is used for printing only, it is the real offset of where the whole instruction begins. + * We need this variable in addition to codeOffset, because prefixes might change the real offset an instruction begins at. + * So we keep track of both. + */ + _OffsetType startInstOffset = 0; + + const uint8_t* p; + + /* Current working decoded instruction in results. */ + unsigned int nextPos = 0; + _DInst *pdi = NULL; + + _OffsetType addrMask = (_OffsetType)-1; + + _DecodeResult decodeResult; + +#ifdef DISTORM_LIGHT + (void) supportOldIntr; /* Unreferenced. */ + + /* + * Only truncate address if we are using the decompose interface. + * Otherwise, we use the textual interface which needs full addresses for formatting bytes output. + * So distorm_format will truncate later. + */ + if (_ci->features & DF_MAXIMUM_ADDR32) addrMask = 0xffffffff; + else if (_ci->features & DF_MAXIMUM_ADDR16) addrMask = 0xffff; +#endif + + /* No entries are used yet. */ + *usedInstructionsCount = 0; + ci.dt = _ci->dt; + _ci->nextOffset = codeOffset; + + /* Decode instructions as long as we have what to decode/enough room in entries. */ + while (codeLen > 0) { + + /* startInstOffset holds the displayed offset of current instruction. */ + startInstOffset = codeOffset; + + COMPAT(memset)(&ps, 0, (size_t)((char*)&ps.pfxIndexer[0] - (char*)&ps)); + COMPAT(memset)(ps.pfxIndexer, PFXIDX_NONE, sizeof(int) * PFXIDX_MAX); + ps.start = code; + ps.last = code; + prefixSize = 0; + + if (prefixes_is_valid(*code, ci.dt)) { + prefixes_decode(code, codeLen, &ps, ci.dt); + /* Count prefixes, start points to first prefix. */ + prefixSize = (unsigned int)(ps.last - ps.start); + /* + * It might be that we will just notice that we ran out of bytes, or only prefixes + * so we will have to drop everything and halt. + * Also take into consideration of flow control instruction filter. + */ + codeLen -= prefixSize; + if ((codeLen == 0) || (prefixSize == INST_MAXIMUM_SIZE)) { + if (~_ci->features & DF_RETURN_FC_ONLY) { + /* Make sure there is enough room. */ + if (nextPos + (ps.last - code) > maxResultCount) return DECRES_MEMORYERR; + + for (p = code; p < ps.last; p++, startInstOffset++) { + /* Use next entry. */ +#ifndef DISTORM_LIGHT + if (supportOldIntr) { + pdi = (_DInst*)((char*)result + nextPos * sizeof(_DecodedInst)); + } + else +#endif /* DISTORM_LIGHT */ + { + pdi = &result[nextPos]; + } + nextPos++; + COMPAT(memset)(pdi, 0, sizeof(_DInst)); + + pdi->flags = FLAG_NOT_DECODABLE; + pdi->imm.byte = *p; + pdi->size = 1; + pdi->addr = startInstOffset & addrMask; + } + *usedInstructionsCount = nextPos; /* Include them all. */ + } + if (codeLen == 0) break; /* Bye bye, out of bytes. */ + } + code += prefixSize; + codeOffset += prefixSize; + + /* If we got only prefixes continue to next instruction. */ + if (prefixSize == INST_MAXIMUM_SIZE) continue; + } + + /* + * Now we decode the instruction and only then we do further prefixes handling. + * This is because the instruction could not be decoded at all, or an instruction requires + * a mandatory prefix, or some of the prefixes were useless, etc... + + * Even if there were a mandatory prefix, we already took into account its size as a normal prefix. + * so prefixSize includes that, and the returned size in pdi is simply the size of the real(=without prefixes) instruction. + */ + if (ci.dt == Decode64Bits) { + if (ps.decodedPrefixes & INST_PRE_REX) { + /* REX prefix must precede first byte of instruction. */ + if (ps.rexPos != (code - 1)) { + ps.decodedPrefixes &= ~INST_PRE_REX; + ps.prefixExtType = PET_NONE; + prefixes_ignore(&ps, PFXIDX_REX); + } + /* + * We will disable operand size prefix, + * if it exists only after decoding the instruction, since it might be a mandatory prefix. + * This will be done after calling inst_lookup in decode_inst. + */ + } + /* In 64 bits, segment overrides of CS, DS, ES and SS are ignored. So don't take'em into account. */ + if (ps.decodedPrefixes & INST_PRE_SEGOVRD_MASK32) { + ps.decodedPrefixes &= ~INST_PRE_SEGOVRD_MASK32; + prefixes_ignore(&ps, PFXIDX_SEG); + } + } + + /* Make sure there is at least one more entry to use, for the upcoming instruction. */ + if (nextPos + 1 > maxResultCount) return DECRES_MEMORYERR; +#ifndef DISTORM_LIGHT + if (supportOldIntr) { + pdi = (_DInst*)((char*)result + nextPos * sizeof(_DecodedInst)); + } + else +#endif /* DISTORM_LIGHT */ + { + pdi = &result[nextPos]; + } + nextPos++; + + /* + * The reason we copy these two again is because we have to keep track on the input ourselves. + * There might be a case when an instruction is invalid, and then it will be counted as one byte only. + * But that instruction already read a byte or two from the stream and only then returned the error. + * Thus, we end up unsynchronized on the stream. + * This way, we are totally safe, because we keep track after the call to decode_inst, using the returned size. + */ + ci.code = code; + ci.codeLen = codeLen; + /* Nobody uses codeOffset in the decoder itself, so spare it. */ + + decodeResult = decode_inst(&ci, &ps, pdi); + + /* See if we need to filter this instruction. */ + if ((_ci->features & DF_RETURN_FC_ONLY) && (META_GET_FC(pdi->meta) == FC_NONE)) decodeResult = DECRES_FILTERED; + + /* Set address to the beginning of the instruction. */ + pdi->addr = startInstOffset & addrMask; + /* pdi->disp &= addrMask; */ + + if ((decodeResult == DECRES_INPUTERR) && (ps.decodedPrefixes & INST_PRE_VEX)) { + if (ps.prefixExtType == PET_VEX3BYTES) { + prefixSize -= 2; + codeLen += 2; + } else if (ps.prefixExtType == PET_VEX2BYTES) { + prefixSize -= 1; + codeLen += 1; + } + ps.last = ps.start + prefixSize - 1; + code = ps.last + 1; + codeOffset = startInstOffset + prefixSize; + } else { + /* Advance to next instruction. */ + codeLen -= pdi->size; + codeOffset += pdi->size; + code += pdi->size; + + /* Instruction's size should include prefixes. */ + pdi->size += (uint8_t)prefixSize; + } + + /* Drop all prefixes and the instruction itself, because the instruction wasn't successfully decoded. */ + if ((decodeResult == DECRES_INPUTERR) && (~_ci->features & DF_RETURN_FC_ONLY)) { + nextPos--; /* Undo last result. */ + if ((prefixSize + 1) > 0) { /* 1 for the first instruction's byte. */ + if ((nextPos + prefixSize + 1) > maxResultCount) return DECRES_MEMORYERR; + + for (p = ps.start; p < ps.last + 1; p++, startInstOffset++) { + /* Use next entry. */ +#ifndef DISTORM_LIGHT + if (supportOldIntr) { + pdi = (_DInst*)((char*)result + nextPos * sizeof(_DecodedInst)); + } + else +#endif /* DISTORM_LIGHT */ + { + pdi = &result[nextPos]; + } + nextPos++; + + COMPAT(memset)(pdi, 0, sizeof(_DInst)); + pdi->flags = FLAG_NOT_DECODABLE; + pdi->imm.byte = *p; + pdi->size = 1; + pdi->addr = startInstOffset & addrMask; + } + } + } else if (decodeResult == DECRES_FILTERED) nextPos--; /* Return it to pool, since it was filtered. */ + + /* Alright, the caller can read, at least, up to this one. */ + *usedInstructionsCount = nextPos; + /* Fix next offset. */ + _ci->nextOffset = codeOffset; + + /* Check whether we need to stop on any flow control instruction. */ + features = _ci->features; + mfc = META_GET_FC(pdi->meta); + if ((decodeResult == DECRES_SUCCESS) && (features & DF_STOP_ON_FLOW_CONTROL)) { + if (((features & DF_STOP_ON_CALL) && (mfc == FC_CALL)) || + ((features & DF_STOP_ON_RET) && (mfc == FC_RET)) || + ((features & DF_STOP_ON_SYS) && (mfc == FC_SYS)) || + ((features & DF_STOP_ON_UNC_BRANCH) && (mfc == FC_UNC_BRANCH)) || + ((features & DF_STOP_ON_CND_BRANCH) && (mfc == FC_CND_BRANCH)) || + ((features & DF_STOP_ON_INT) && (mfc == FC_INT)) || + ((features & DF_STOP_ON_CMOV) && (mfc == FC_CMOV))) + return DECRES_SUCCESS; + } + } + + return DECRES_SUCCESS; +} diff --git a/source/distorm/decoder.h b/source/distorm/decoder.h new file mode 100644 index 0000000..2f9961a --- /dev/null +++ b/source/distorm/decoder.h @@ -0,0 +1,33 @@ +/* +decoder.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2011 Gil Dabah + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see <http://www.gnu.org/licenses/> +*/ + + +#ifndef DECODER_H +#define DECODER_H + +#include "config.h" + +typedef unsigned int _iflags; + +_DecodeResult decode_internal(_CodeInfo* ci, int supportOldIntr, _DInst result[], unsigned int maxResultCount, unsigned int* usedInstructionsCount); + +#endif /* DECODER_H */ diff --git a/source/distorm/distorm.c b/source/distorm/distorm.c new file mode 100644 index 0000000..94279e6 --- /dev/null +++ b/source/distorm/distorm.c @@ -0,0 +1,409 @@ +/* +distorm.c + +diStorm3 C Library Interface +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "distorm/distorm.h" +#include "config.h" +#include "decoder.h" +#include "x86defs.h" +#include "textdefs.h" +#include "wstring.h" +#include "distorm/mnemonics.h" +#include "compat.h" + +/* C DLL EXPORTS */ +#ifdef SUPPORT_64BIT_OFFSET + _DLLEXPORT_ _DecodeResult distorm_decompose64(_CodeInfo* ci, _DInst result[], unsigned int maxInstructions, unsigned int* usedInstructionsCount) +#else + _DLLEXPORT_ _DecodeResult distorm_decompose32(_CodeInfo* ci, _DInst result[], unsigned int maxInstructions, unsigned int* usedInstructionsCount) +#endif +{ + if (usedInstructionsCount == NULL) { + return DECRES_SUCCESS; + } + + /* DECRES_SUCCESS still may indicate we may have something in the result, so zero it first thing. */ + *usedInstructionsCount = 0; + + if ((ci == NULL) || + (ci->codeLen < 0) || + ((ci->dt != Decode16Bits) && (ci->dt != Decode32Bits) && (ci->dt != Decode64Bits)) || + (ci->code == NULL) || + (result == NULL) || + ((ci->features & (DF_MAXIMUM_ADDR16 | DF_MAXIMUM_ADDR32)) == (DF_MAXIMUM_ADDR16 | DF_MAXIMUM_ADDR32))) + { + return DECRES_INPUTERR; + } + + /* Assume length=0 is success. */ + if (ci->codeLen == 0) { + return DECRES_SUCCESS; + } + + return decode_internal(ci, FALSE, result, maxInstructions, usedInstructionsCount); +} + +#ifndef DISTORM_LIGHT + +/* Helper function to concatenate an explicit size when it's unknown from the operands. */ +static void distorm_format_size(_WString* str, const _DInst* di, int opNum) +{ + int isSizingRequired = 0; + /* + * We only have to output the size explicitly if it's not clear from the operands. + * For example: + * mov al, [0x1234] -> The size is 8, we know it from the AL register operand. + * mov [0x1234], 0x11 -> Now we don't know the size. Pam pam pam + * + * If given operand number is higher than 2, then output the size anyways. + */ + isSizingRequired = ((opNum >= 2) || ((di->ops[0].type != O_REG) && (di->ops[1].type != O_REG))); + + /* Still not sure? Try some special instructions. */ + if (!isSizingRequired) { + /* + * INS/OUTS are exception, because DX is a port specifier and not a real src/dst register. + * A few exceptions that always requires sizing: + * MOVZX, MOVSX, MOVSXD. + * ROL, ROR, RCL, RCR, SHL, SHR, SAL, SAR. + * SHLD, SHRD. + */ + switch (di->opcode) + { + case I_INS: + case I_OUTS: + case I_MOVZX: + case I_MOVSX: + case I_MOVSXD: + case I_ROL: + case I_ROR: + case I_RCL: + case I_RCR: + case I_SHL: + case I_SHR: + case I_SAL: + case I_SAR: + case I_SHLD: + case I_SHRD: + isSizingRequired = 1; + break; + default: /* Instruction doesn't require sizing. */ break; + } + } + + if (isSizingRequired) + { + switch (di->ops[opNum].size) + { + case 0: break; /* OT_MEM's unknown size. */ + case 8: strcat_WSN(str, "BYTE "); break; + case 16: strcat_WSN(str, "WORD "); break; + case 32: strcat_WSN(str, "DWORD "); break; + case 64: strcat_WSN(str, "QWORD "); break; + case 80: strcat_WSN(str, "TBYTE "); break; + case 128: strcat_WSN(str, "DQWORD "); break; + case 256: strcat_WSN(str, "YWORD "); break; + default: /* Big oh uh if it gets here. */ break; + } + } +} + +static void distorm_format_signed_disp(_WString* str, const _DInst* di, uint64_t addrMask) +{ + int64_t tmpDisp64; + + if (di->dispSize) { + chrcat_WS(str, ((int64_t)di->disp < 0) ? MINUS_DISP_CHR : PLUS_DISP_CHR); + if ((int64_t)di->disp < 0) tmpDisp64 = -(int64_t)di->disp; + else tmpDisp64 = di->disp; + tmpDisp64 &= addrMask; + str_code_hqw(str, (uint8_t*)&tmpDisp64); + } +} + +#ifdef SUPPORT_64BIT_OFFSET + _DLLEXPORT_ void distorm_format64(const _CodeInfo* ci, const _DInst* di, _DecodedInst* result) +#else + _DLLEXPORT_ void distorm_format32(const _CodeInfo* ci, const _DInst* di, _DecodedInst* result) +#endif +{ + _WString* str; + unsigned int i, isDefault; + int64_t tmpDisp64; + uint64_t addrMask = (uint64_t)-1; + uint8_t segment; + const _WMnemonic* mnemonic; + + /* Set address mask, when default is for 64bits addresses. */ + if (ci->features & DF_MAXIMUM_ADDR32) addrMask = 0xffffffff; + else if (ci->features & DF_MAXIMUM_ADDR16) addrMask = 0xffff; + + /* Copy other fields. */ + result->size = di->size; + result->offset = di->addr; + + if (di->flags == FLAG_NOT_DECODABLE) { + str = &result->mnemonic; + result->offset &= addrMask; + strclear_WS(&result->operands); + strcpy_WSN(str, "DB "); + str_code_hb(str, di->imm.byte); + strclear_WS(&result->instructionHex); + str_hex_b(&result->instructionHex, di->imm.byte); + return; /* Skip to next instruction. */ + } + + str = &result->instructionHex; + strclear_WS(str); + /* Gotta have full address for (di->addr - ci->codeOffset) to work in all modes. */ + for (i = 0; i < di->size; i++) + str_hex_b(str, ci->code[(unsigned int)(di->addr - ci->codeOffset + i)]); + + /* Truncate address now. */ + result->offset &= addrMask; + + str = &result->mnemonic; + switch (FLAG_GET_PREFIX(di->flags)) + { + case FLAG_LOCK: + strcpy_WSN(str, "LOCK "); + break; + case FLAG_REP: + /* REP prefix for CMPS and SCAS is really a REPZ. */ + if ((di->opcode == I_CMPS) || (di->opcode == I_SCAS)) strcpy_WSN(str, "REPZ "); + else strcpy_WSN(str, "REP "); + break; + case FLAG_REPNZ: + strcpy_WSN(str, "REPNZ "); + break; + default: + /* Init mnemonic string, cause next touch is concatenation. */ + strclear_WS(str); + break; + } + + mnemonic = (const _WMnemonic*)&_MNEMONICS[di->opcode]; + COMPAT(memcpy)((int8_t*)&str->p[str->length], mnemonic->p, mnemonic->length + 1); + str->length += mnemonic->length; + + /* Format operands: */ + str = &result->operands; + strclear_WS(str); + + /* Special treatment for String instructions. */ + if ((META_GET_ISC(di->meta) == ISC_INTEGER) && + ((di->opcode == I_MOVS) || + (di->opcode == I_CMPS) || + (di->opcode == I_STOS) || + (di->opcode == I_LODS) || + (di->opcode == I_SCAS))) + { + /* + * No operands are needed if the address size is the default one, + * and no segment is overridden, so add the suffix letter, + * to indicate size of operation and continue to next instruction. + */ + if ((FLAG_GET_ADDRSIZE(di->flags) == ci->dt) && (SEGMENT_IS_DEFAULT(di->segment))) { + str = &result->mnemonic; + switch (di->ops[0].size) + { + case 8: chrcat_WS(str, 'B'); break; + case 16: chrcat_WS(str, 'W'); break; + case 32: chrcat_WS(str, 'D'); break; + case 64: chrcat_WS(str, 'Q'); break; + } + return; + } + } + + for (i = 0; ((i < OPERANDS_NO) && (di->ops[i].type != O_NONE)); i++) { + if (i > 0) strcat_WSN(str, ", "); + switch (di->ops[i].type) + { + case O_REG: + strcat_WS(str, (const _WString*)&_REGISTERS[di->ops[i].index]); + break; + case O_IMM: + /* If the instruction is 'push', show explicit size (except byte imm). */ + if ((di->opcode == I_PUSH) && (di->ops[i].size != 8)) distorm_format_size(str, di, i); + /* Special fix for negative sign extended immediates. */ + if ((di->flags & FLAG_IMM_SIGNED) && (di->ops[i].size == 8)) { + if (di->imm.sbyte < 0) { + chrcat_WS(str, MINUS_DISP_CHR); + str_code_hb(str, -di->imm.sbyte); + break; + } + } + if (di->ops[i].size == 64) str_code_hqw(str, (uint8_t*)&di->imm.qword); + else str_code_hdw(str, di->imm.dword); + break; + case O_IMM1: + str_code_hdw(str, di->imm.ex.i1); + break; + case O_IMM2: + str_code_hdw(str, di->imm.ex.i2); + break; + case O_DISP: + distorm_format_size(str, di, i); + chrcat_WS(str, OPEN_CHR); + if ((SEGMENT_GET(di->segment) != R_NONE) && !SEGMENT_IS_DEFAULT(di->segment)) { + strcat_WS(str, (const _WString*)&_REGISTERS[SEGMENT_GET(di->segment)]); + chrcat_WS(str, SEG_OFF_CHR); + } + tmpDisp64 = di->disp & addrMask; + str_code_hqw(str, (uint8_t*)&tmpDisp64); + chrcat_WS(str, CLOSE_CHR); + break; + case O_SMEM: + distorm_format_size(str, di, i); + chrcat_WS(str, OPEN_CHR); + + /* + * This is where we need to take special care for String instructions. + * If we got here, it means we need to explicitly show their operands. + * The problem with CMPS and MOVS is that they have two(!) memory operands. + * So we have to complete it ourselves, since the structure supplies only the segment that can be overridden. + * And make the rest of the String operations explicit. + */ + segment = SEGMENT_GET(di->segment); + isDefault = SEGMENT_IS_DEFAULT(di->segment); + switch (di->opcode) + { + case I_MOVS: + isDefault = FALSE; + if (i == 0) segment = R_ES; + break; + case I_CMPS: + isDefault = FALSE; + if (i == 1) segment = R_ES; + break; + case I_INS: + case I_LODS: + case I_STOS: + case I_SCAS: isDefault = FALSE; break; + } + if (!isDefault && (segment != R_NONE)) { + strcat_WS(str, (const _WString*)&_REGISTERS[segment]); + chrcat_WS(str, SEG_OFF_CHR); + } + + strcat_WS(str, (const _WString*)&_REGISTERS[di->ops[i].index]); + + distorm_format_signed_disp(str, di, addrMask); + chrcat_WS(str, CLOSE_CHR); + break; + case O_MEM: + distorm_format_size(str, di, i); + chrcat_WS(str, OPEN_CHR); + if ((SEGMENT_GET(di->segment) != R_NONE) && !SEGMENT_IS_DEFAULT(di->segment)) { + strcat_WS(str, (const _WString*)&_REGISTERS[SEGMENT_GET(di->segment)]); + chrcat_WS(str, SEG_OFF_CHR); + } + if (di->base != R_NONE) { + strcat_WS(str, (const _WString*)&_REGISTERS[di->base]); + chrcat_WS(str, PLUS_DISP_CHR); + } + strcat_WS(str, (const _WString*)&_REGISTERS[di->ops[i].index]); + if (di->scale != 0) { + chrcat_WS(str, '*'); + if (di->scale == 2) chrcat_WS(str, '2'); + else if (di->scale == 4) chrcat_WS(str, '4'); + else /* if (di->scale == 8) */ chrcat_WS(str, '8'); + } + + distorm_format_signed_disp(str, di, addrMask); + chrcat_WS(str, CLOSE_CHR); + break; + case O_PC: +#ifdef SUPPORT_64BIT_OFFSET + str_off64(str, (di->imm.sqword + di->addr + di->size) & addrMask); +#else + str_code_hdw(str, ((_OffsetType)di->imm.sdword + di->addr + di->size) & (uint32_t)addrMask); +#endif + break; + case O_PTR: + str_code_hdw(str, di->imm.ptr.seg); + chrcat_WS(str, SEG_OFF_CHR); + str_code_hdw(str, di->imm.ptr.off); + break; + } + } + + if (di->flags & FLAG_HINT_TAKEN) strcat_WSN(str, " ;TAKEN"); + else if (di->flags & FLAG_HINT_NOT_TAKEN) strcat_WSN(str, " ;NOT TAKEN"); +} + +#ifdef SUPPORT_64BIT_OFFSET + _DLLEXPORT_ _DecodeResult distorm_decode64(_OffsetType codeOffset, const unsigned char* code, int codeLen, _DecodeType dt, _DecodedInst result[], unsigned int maxInstructions, unsigned int* usedInstructionsCount) +#else + _DLLEXPORT_ _DecodeResult distorm_decode32(_OffsetType codeOffset, const unsigned char* code, int codeLen, _DecodeType dt, _DecodedInst result[], unsigned int maxInstructions, unsigned int* usedInstructionsCount) +#endif +{ + _DecodeResult res; + _DInst di; + _CodeInfo ci; + unsigned int instsCount = 0, i; + + *usedInstructionsCount = 0; + + /* I use codeLen as a signed variable in order to ease detection of underflow... and besides - */ + if (codeLen < 0) { + return DECRES_INPUTERR; + } + + if ((dt != Decode16Bits) && (dt != Decode32Bits) && (dt != Decode64Bits)) { + return DECRES_INPUTERR; + } + + if (code == NULL || result == NULL) { + return DECRES_INPUTERR; + } + + /* Assume length=0 is success. */ + if (codeLen == 0) { + return DECRES_SUCCESS; + } + + /* + * We have to format the result into text. But the interal decoder works with the new structure of _DInst. + * Therefore, we will pass the result array(!) from the caller and the interal decoder will fill it in with _DInst's. + * Then we will copy each result to a temporary structure, and use it to reformat that specific result. + * + * This is all done to save memory allocation and to work on the same result array in-place!!! + * It's a bit ugly, I have to admit, but worth it. + */ + + ci.codeOffset = codeOffset; + ci.code = code; + ci.codeLen = codeLen; + ci.dt = dt; + ci.features = DF_NONE; + if (dt == Decode16Bits) ci.features = DF_MAXIMUM_ADDR16; + else if (dt == Decode32Bits) ci.features = DF_MAXIMUM_ADDR32; + + res = decode_internal(&ci, TRUE, (_DInst*)result, maxInstructions, &instsCount); + for (i = 0; i < instsCount; i++) { + if ((*usedInstructionsCount + i) >= maxInstructions) return DECRES_MEMORYERR; + + /* Copy the current decomposed result to a temp structure, so we can override the result with text. */ + COMPAT(memcpy)(&di, (char*)result + (i * sizeof(_DecodedInst)), sizeof(_DInst)); +#ifdef SUPPORT_64BIT_OFFSET + distorm_format64(&ci, &di, &result[i]); +#else + distorm_format32(&ci, &di, &result[i]); +#endif + } + + *usedInstructionsCount = instsCount; + return res; +} + +#endif /* DISTORM_LIGHT */ diff --git a/source/distorm/instructions.c b/source/distorm/instructions.c new file mode 100644 index 0000000..5c1561b --- /dev/null +++ b/source/distorm/instructions.c @@ -0,0 +1,598 @@ +/* +instructions.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "instructions.h" + +#include "insts.h" +#include "prefix.h" +#include "x86defs.h" +#include "distorm/mnemonics.h" +#include "compat.h" + + +/* Helper macros to extract the type or index from an inst-node value. */ +#define INST_NODE_INDEX(n) ((n) & 0x1fff) +#define INST_NODE_TYPE(n) ((n) >> 13) + +/* Helper macro to read the actual flags that are associated with an inst-info. */ +#define INST_INFO_FLAGS(ii) (FlagsTable[InstSharedInfoTable[(ii)->sharedIndex].flagsIndex]) + +/* +I use the trie data structure as I found it most fitting to a disassembler mechanism. +When you read a byte and have to decide if it's enough or you should read more bytes, 'till you get to the instruction information. +It's really fast because you POP the instruction info in top 3 iterates on the DB, because an instruction can be formed from two bytes + 3 bits reg from the ModR/M byte. +For a simple explanation, check this out: +http://www.csse.monash.edu.au/~lloyd/tildeAlgDS/Tree/Trie/ +Further reading: http://en.wikipedia.org/wiki/Trie + +The first GATE (array you read off a trie data structure), as I call them, is statically allocated by the compiler. +The second and third gates if used are being allocated dynamically by the instructions-insertion functionality. + +How would such a thing look in memory, say we support 4 instructions with 3 bytes top (means 2 dynamically allocated gates). + +-> +|-------| 0, +|0| -------------------------------> |-------| +|1|RET | 1, |0|AND | +|2| -----> |-------| |1|XOR | +|3|INT3 | |0|PUSH | |2|OR | 0,3, +|-------| |1|POP | |3| --------->|-------| + |2|PUSHF| |-------| |0|ROR | + |3|POPF | |1|ROL | + |-------| |2|SHR | + |3|SHL | + |-------| + +Of course, this is NOT how Intel instructions set looks!!! +but I just wanted to give a small demonstration. +Now the instructions you get from such a trie DB goes like this: + +0, 0 - AND +0, 1 - XOR +0, 2 - OR +0, 3, 0, ROR +0, 3, 1, ROL +0, 3, 2, SHR +0, 3, 3, SHL +1 - RET +2, 0 - PUSH +2, 1 - POP +2, 2 - PUSHF +2, 3 - POPF +3 - INT3 + +I guess it's clear by now. +So now, if you read 0, you know that you have to enter the second gate(list) with the second byte specifying the index. +But if you read 1, you know that you go to an instruction (in this case, a RET). +That's why there's an Instruction-Node structure, it tells you whether you got to an instruction or another list +so you should keep on reading byte). + +In Intel, you could go through 4 gates at top, because there are instructions which are built from 2 bytes and another smaller list +for the REG part, or newest SSE4 instructions which use 4 bytes for opcode. +Therefore, Intel's first gate is 256 long, and other gates are 256 (/72) or 8 long, yes, it costs pretty much a lot of memory +for non-used defined instructions, but I think that it still rocks. +*/ + +/* + * A helper function to look up the correct inst-info structure. + * It does one fetch from the index-table, and then another to get the inst-info. + * Note that it takes care about basic inst-info or inst-info-ex. + * The caller should worry about boundary checks and whether it accesses a last-level table. + */ +static _InstInfo* inst_get_info(_InstNode in, int index) +{ + int instIndex = 0; + + in = InstructionsTree[INST_NODE_INDEX(in) + index]; + if (in == INT_NOTEXISTS) return NULL; + + instIndex = INST_NODE_INDEX(in); + return INST_NODE_TYPE(in) == INT_INFO ? &InstInfos[instIndex] : (_InstInfo*)&InstInfosEx[instIndex]; +} + +/* + * This function is responsible to return the instruction information of the first found in code. + * It returns the _InstInfo of the found instruction, otherwise NULL. + * code should point to the ModR/M byte upon exit (if used), or after the instruction binary code itself. + * This function is NOT decoding-type dependant, it is up to the caller to see whether the instruction is valid. + * Get the instruction info, using a Trie data structure. + * + * Sometimes normal prefixes become mandatory prefixes, which means they are now part of the instruction opcode bytes. + + * This is a bit tricky now, + * if the first byte is a REP (F3) prefix, we will have to give a chance to an SSE instruction. + * If an instruction doesn't exist, we will make it as a prefix and re-locateinst. + * A case such that a REP prefix is being changed into an instruction byte and also an SSE instruction will not be found can't happen, + * simply because there are no collisions between string instruction and SSE instructions (they are escaped). + + * As for S/SSE2/3, check for F2 and 66 as well. + + * In 64 bits, we have to make sure that we will skip the REX prefix, if it exists. + * There's a specific case, where a 66 is mandatory but it was dropped because REG.W was used, + * but it doesn't behave as an operand size prefix but as a mandatory, so we will have to take it into account. + + * For example (64 bits decoding mode): + * 66 98 CBW + * 48 98 CDQE + * 66 48 98: db 0x66; CDQE + * Shows that operand size is dropped. + + * Now, it's a mandatory prefix and NOT an operand size one. + * 66480f2dc0 db 0x48; CVTPD2PI XMM0, XMM0 + * Although this instruction doesn't require a REX.W, it just shows, that even if it did - it doesn't matter. + * REX.W is dropped because it's not required, but the decode function disabled the operand size even so. + */ +static _InstInfo* inst_lookup_prefixed(_InstNode in, _PrefixState* ps) +{ + int checkOpSize = FALSE; + int index = 0; + _InstInfo* ii = NULL; + + /* Check prefixes of current decoded instruction (None, 0x66, 0xf3, 0xf2). */ + switch (ps->decodedPrefixes & (INST_PRE_OP_SIZE | INST_PRE_REPS)) + { + case 0: + /* Non-prefixed, index = 0. */ + index = 0; + break; + case INST_PRE_OP_SIZE: + /* 0x66, index = 1. */ + index = 1; + /* Mark that we used it as a mandatory prefix. */ + ps->isOpSizeMandatory = TRUE; + ps->decodedPrefixes &= ~INST_PRE_OP_SIZE; + break; + case INST_PRE_REP: + /* 0xf3, index = 2. */ + index = 2; + ps->decodedPrefixes &= ~INST_PRE_REP; + break; + case INST_PRE_REPNZ: + /* 0xf2, index = 3. */ + index = 3; + ps->decodedPrefixes &= ~INST_PRE_REPNZ; + break; + default: + /* + * Now we got a problem, since there are a few mandatory prefixes at once. + * There is only one case when it's ok, when the operand size prefix is for real (not mandatory). + * Otherwise we will have to return NULL, since the instruction is illegal. + * Therefore we will start with REPNZ and REP prefixes, + * try to get the instruction and only then check for the operand size prefix. + */ + + /* If both REPNZ and REP are together, it's illegal for sure. */ + if ((ps->decodedPrefixes & INST_PRE_REPS) == INST_PRE_REPS) return NULL; + + /* Now we know it's either REPNZ+OPSIZE or REP+OPSIZE, so examine the instruction. */ + if (ps->decodedPrefixes & INST_PRE_REPNZ) { + index = 3; + ps->decodedPrefixes &= ~INST_PRE_REPNZ; + } else if (ps->decodedPrefixes & INST_PRE_REP) { + index = 2; + ps->decodedPrefixes &= ~INST_PRE_REP; + } + /* Mark to verify the operand-size prefix of the fetched instruction below. */ + checkOpSize = TRUE; + break; + } + + /* Fetch the inst-info from the index. */ + ii = inst_get_info(in, index); + + if (checkOpSize) { + /* If the instruction doesn't support operand size prefix, then it's illegal. */ + if ((ii == NULL) || (~INST_INFO_FLAGS(ii) & INST_PRE_OP_SIZE)) return NULL; + } + + /* If there was a prefix, but the instruction wasn't found. Try to fall back to use the normal instruction. */ + if (ii == NULL) ii = inst_get_info(in, 0); + return ii; +} + +/* A helper function to look up special VEX instructions. + * See if it's a MOD based instruction and fix index if required. + * Only after a first lookup (that was done by caller), we can tell if we need to fix the index. + * Because these are coupled instructions + * (which means that the base instruction hints about the other instruction). + * Note that caller should check if it's a MOD dependent instruction before getting in here. + */ +static _InstInfo* inst_vex_mod_lookup(_CodeInfo* ci, _InstNode in, _InstInfo* ii, unsigned int index) +{ + /* Advance to read the MOD from ModRM byte. */ + ci->code += 1; + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + if (*ci->code < INST_DIVIDED_MODRM) { + /* MOD is not 11, therefore change the index to 8 - 12 range in the prefixed table. */ + index += 4; + /* Make a second lookup for this special instruction. */ + return inst_get_info(in, index); + } + /* Return the original one, in case we didn't find a suited instruction. */ + return ii; +} + +static _InstInfo* inst_vex_lookup(_CodeInfo* ci, _PrefixState* ps) +{ + _InstNode in = 0; + unsigned int pp = 0, start = 0; + unsigned int index = 4; /* VEX instructions start at index 4 in the Prefixed table. */ + uint8_t vex = *ps->vexPos, vex2 = 0, v = 0; + int instType = 0, instIndex = 0; + + /* The VEX instruction will #ud if any of 66, f0, f2, f3, REX prefixes precede. */ + _iflags illegal = (INST_PRE_OP_SIZE | INST_PRE_LOCK | INST_PRE_REP | INST_PRE_REPNZ | INST_PRE_REX); + if ((ps->decodedPrefixes & illegal) != 0) return NULL; + + /* Read the some fields from the VEX prefix we need to extract the instruction. */ + if (ps->prefixExtType == PET_VEX2BYTES) { + ps->vexV = v = (~vex >> 3) & 0xf; + pp = vex & 3; + /* Implied leading 0x0f byte by default for 2 bytes VEX prefix. */ + start = 1; + } else { /* PET_VEX3BYTES */ + start = vex & 0x1f; + vex2 = *(ps->vexPos + 1); + ps->vexV = v = (~vex2 >> 3) & 0xf; + pp = vex2 & 3; + } + + /* start can be either 1 (0x0f), 2 (0x0f, 0x038) or 3 (0x0f, 0x3a), otherwise it's illegal. */ + switch (start) + { + case 1: in = Table_0F; break; + case 2: in = Table_0F_38; break; + case 3: in = Table_0F_3A; break; + default: return NULL; + } + + /* pp is actually the implied mandatory prefix, apply it to the index. */ + index += pp; /* (None, 0x66, 0xf3, 0xf2) */ + + /* Read a byte from the stream. */ + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + + in = InstructionsTree[INST_NODE_INDEX(in) + *ci->code]; + if (in == INT_NOTEXISTS) return NULL; + + instType = INST_NODE_TYPE(in); + instIndex = INST_NODE_INDEX(in); + + /* + * If we started with 0f38 or 0f3a so it's a prefixed table, + * therefore it's surely a VEXed instruction (because of a high index). + * However, starting with 0f, could also lead immediately to a prefixed table for some bytes. + * it might return NULL, if the index is invalid. + */ + if (instType == INT_LIST_PREFIXED) { + _InstInfo* ii = inst_get_info(in, index); + /* See if the instruction is dependent on MOD. */ + if ((ii != NULL) && (((_InstInfoEx*)ii)->flagsEx & INST_MODRR_BASED)) { + ii = inst_vex_mod_lookup(ci, in, ii, index); + } + return ii; + } + + /* + * If we reached here, obviously we started with 0f. VEXed instructions must be nodes of a prefixed table. + * But since we found an instruction (or divided one), just return NULL. + * They cannot lead to a VEXed instruction. + */ + if ((instType == INT_INFO) || (instType == INT_INFOEX) || (instType == INT_LIST_DIVIDED)) return NULL; + + /* Now we are left with handling either GROUP or FULL tables, therefore we will read another byte from the stream. */ + ci->code += 1; + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + + if (instType == INT_LIST_GROUP) { + in = InstructionsTree[instIndex + ((*ci->code >> 3) & 7)]; + /* Continue below to check prefixed table. */ + } else if (instType == INT_LIST_FULL) { + in = InstructionsTree[instIndex + *ci->code]; + /* Continue below to check prefixed table. */ + } + + /* Now that we got to the last table in the trie, check for a prefixed table. */ + if (INST_NODE_TYPE(in) == INT_LIST_PREFIXED) { + _InstInfo* ii = inst_get_info(in, index); + /* See if the instruction is dependent on MOD. */ + if ((ii != NULL) && (((_InstInfoEx*)ii)->flagsEx & INST_MODRR_BASED)) { + ii = inst_vex_mod_lookup(ci, in, ii, index); + } + return ii; + } + + /* No VEXed instruction was found. */ + return NULL; +} + +_InstInfo* inst_lookup(_CodeInfo* ci, _PrefixState* ps) +{ + unsigned int tmpIndex0 = 0, tmpIndex1 = 0, tmpIndex2 = 0, rex = ps->vrex; + int instType = 0; + _InstNode in = 0; + _InstInfo* ii = NULL; + int isWaitIncluded = FALSE; + + /* See whether we have to handle a VEX prefixed instruction. */ + if (ps->decodedPrefixes & INST_PRE_VEX) { + ii = inst_vex_lookup(ci, ps); + if (ii != NULL) { + /* Make sure that VEX.L exists when forced. */ + if ((((_InstInfoEx*)ii)->flagsEx & INST_FORCE_VEXL) && (~ps->vrex & PREFIX_EX_L)) return NULL; + /* If the instruction doesn't use VEX.vvvv it must be zero. */ + if ((((_InstInfoEx*)ii)->flagsEx & INST_VEX_V_UNUSED) && ps->vexV) return NULL; + } + return ii; + } + + /* Read first byte. */ + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + tmpIndex0 = *ci->code; + + /* Check for special 0x9b, WAIT instruction, which can be part of some instructions(x87). */ + if (tmpIndex0 == INST_WAIT_INDEX) { + /* Only OCST_1dBYTES get a chance to include this byte as part of the opcode. */ + isWaitIncluded = TRUE; + + /* Ignore all prefixes, since they are useless and operate on the WAIT instruction itself. */ + prefixes_ignore_all(ps); + + /* Move to next code byte as a new whole instruction. */ + ci->code += 1; + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; /* Faster to return NULL, it will be detected as WAIT later anyway. */ + /* Since we got a WAIT prefix, we re-read the first byte. */ + tmpIndex0 = *ci->code; + } + + /* Walk first byte in InstructionsTree root. */ + in = InstructionsTree[tmpIndex0]; + if (in == INT_NOTEXISTS) return NULL; + instType = INST_NODE_TYPE(in); + + /* Single byte instruction (OCST_1BYTE). */ + if ((instType < INT_INFOS) && (!isWaitIncluded)) { + /* Some single byte instructions need extra treatment. */ + switch (tmpIndex0) + { + case INST_ARPL_INDEX: + /* + * ARPL/MOVSXD share the same opcode, and both have different operands and mnemonics, of course. + * Practically, I couldn't come up with a comfortable way to merge the operands' types of ARPL/MOVSXD. + * And since the DB can't be patched dynamically, because the DB has to be multi-threaded compliant, + * I have no choice but to check for ARPL/MOVSXD right here - "right about now, the funk soul brother, check it out now, the funk soul brother...", fatboy slim + */ + if (ci->dt == Decode64Bits) { + return &II_MOVSXD; + } /* else ARPL will be returned because its defined in the DB already. */ + break; + + case INST_NOP_INDEX: /* Nopnopnop */ + /* Check for Pause, since it's prefixed with 0xf3, which is not a real mandatory prefix. */ + if (ps->decodedPrefixes & INST_PRE_REP) { + /* Flag this prefix as used. */ + ps->usedPrefixes |= INST_PRE_REP; + return &II_PAUSE; + } + + /* + * Treat NOP/XCHG specially. + * If we're not in 64bits restore XCHG to NOP, since in the DB it's XCHG. + * Else if we're in 64bits examine REX, if exists, and decide which instruction should go to output. + * 48 90 XCHG RAX, RAX is a true NOP (eat REX in this case because it's valid). + * 90 XCHG EAX, EAX is a true NOP (and not high dword of RAX = 0 although it should be a 32 bits operation). + * Note that if the REX.B is used, then the register is not RAX anymore but R8, which means it's not a NOP. + */ + if (rex & PREFIX_EX_W) ps->usedPrefixes |= INST_PRE_REX; + if ((ci->dt != Decode64Bits) || (~rex & PREFIX_EX_B)) return &II_NOP; + break; + + case INST_LEA_INDEX: + /* Ignore segment override prefixes for LEA instruction. */ + ps->decodedPrefixes &= ~INST_PRE_SEGOVRD_MASK; + /* Update unused mask for ignoring segment prefix. */ + prefixes_ignore(ps, PFXIDX_SEG); + break; + } + + /* Return the 1 byte instruction we found. */ + return instType == INT_INFO ? &InstInfos[INST_NODE_INDEX(in)] : (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in)]; + } + + /* Read second byte, still doesn't mean all of its bits are used (I.E: ModRM). */ + ci->code += 1; + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + tmpIndex1 = *ci->code; + + /* Try single byte instruction + reg bits (OCST_13BYTES). */ + if ((instType == INT_LIST_GROUP) && (!isWaitIncluded)) return inst_get_info(in, (tmpIndex1 >> 3) & 7); + + /* Try single byte instruction + reg byte OR one whole byte (OCST_1dBYTES). */ + if (instType == INT_LIST_DIVIDED) { + + /* Checking for inst by REG bits is higher priority if it's found not to be divided instruction. */ + { + _InstNode in2 = InstructionsTree[INST_NODE_INDEX(in) + ((tmpIndex1 >> 3) & 7)]; + /* + * Do NOT check for NULL here, since we do a bit of a guess work, + * hence we don't override 'in', cause we might still need it. + */ + instType = INST_NODE_TYPE(in2); + + if (instType == INT_INFO) ii = &InstInfos[INST_NODE_INDEX(in2)]; + else if (instType == INT_INFOEX) ii = (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in2)]; + if ((ii != NULL) && (INST_INFO_FLAGS(ii) & INST_NOT_DIVIDED)) return ii; + /* ii is reset below. */ + } + + /* Continue normally because of wait prefix. */ + if (tmpIndex1 < INST_DIVIDED_MODRM) { + /* An instruction which requires a ModR/M byte. Thus it's 1.3 bytes long instruction. */ + tmpIndex1 = (tmpIndex1 >> 3) & 7; /* Isolate the 3 REG/OPCODE bits. */ + } else { /* Normal 2 bytes instruction. */ + /* + * Divided instructions can't be in the range of 0x8-0xc0. + * That's because 0-8 are used for 3 bits group. + * And 0xc0-0xff are used for not-divided instruction. + * So the in between range is omitted, thus saving some more place in the tables. + */ + tmpIndex1 -= INST_DIVIDED_MODRM - 8; + } + + in = InstructionsTree[INST_NODE_INDEX(in) + tmpIndex1]; + if (in == INT_NOTEXISTS) return NULL; + instType = INST_NODE_TYPE(in); + + if (instType < INT_INFOS) { + /* If the instruction doesn't support the wait (marked as opsize) as part of the opcode, it's illegal. */ + ii = instType == INT_INFO ? &InstInfos[INST_NODE_INDEX(in)] : (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in)]; + if ((~INST_INFO_FLAGS(ii) & INST_PRE_OP_SIZE) && (isWaitIncluded)) return NULL; + return ii; + } + /* + * If we got here the instruction can support the wait prefix, so see if it was part of the stream. + * Examine prefixed table, specially used for 0x9b, since it's optional. + * No Wait: index = 0. + * Wait Exists, index = 1. + */ + return inst_get_info(in, isWaitIncluded); + } + + /* Don't allow to continue if WAIT is part of the opcode, because there are no instructions that include it. */ + if (isWaitIncluded) return NULL; + + /* Try 2 bytes long instruction (doesn't include ModRM byte). */ + if (instType == INT_LIST_FULL) { + in = InstructionsTree[INST_NODE_INDEX(in) + tmpIndex1]; + if (in == INT_NOTEXISTS) return NULL; + instType = INST_NODE_TYPE(in); + + /* This is where we check if we just read two escape bytes in a row, which means it is a 3DNow! instruction. */ + if ((tmpIndex0 == _3DNOW_ESCAPE_BYTE) && (tmpIndex1 == _3DNOW_ESCAPE_BYTE)) return &II_3DNOW; + + /* 2 bytes instruction (OCST_2BYTES). */ + if (instType < INT_INFOS) + return instType == INT_INFO ? &InstInfos[INST_NODE_INDEX(in)] : (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in)]; + + /* + * 2 bytes + mandatory prefix. + * Mandatory prefixes can be anywhere in the prefixes. + * There cannot be more than one mandatory prefix, unless it's a normal operand size prefix. + */ + if (instType == INT_LIST_PREFIXED) return inst_lookup_prefixed(in, ps); + } + + /* Read third byte, still doesn't mean all of its bits are used (I.E: ModRM). */ + ci->code += 1; + ci->codeLen -= 1; + if (ci->codeLen < 0) return NULL; + tmpIndex2 = *ci->code; + + /* Try 2 bytes + reg instruction (OCST_23BYTES). */ + if (instType == INT_LIST_GROUP) { + in = InstructionsTree[INST_NODE_INDEX(in) + ((tmpIndex2 >> 3) & 7)]; + if (in == INT_NOTEXISTS) return NULL; + instType = INST_NODE_TYPE(in); + + if (instType < INT_INFOS) + return instType == INT_INFO ? &InstInfos[INST_NODE_INDEX(in)] : (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in)]; + + /* It has to be a prefixed table then. */ + ii = inst_lookup_prefixed(in, ps); + /* RDRAND and VMPTRLD share same 2.3 bytes opcode, and alternate on the MOD bits. See insts.h for more info. */ + if ((ii != NULL) && (ii->opcodeId == I_VMPTRLD) && (tmpIndex1 >= INST_DIVIDED_MODRM)) return &II_RDRAND; + return ii; + } + + /* Try 2 bytes + divided range (OCST_2dBYTES). */ + if (instType == INT_LIST_DIVIDED) { + _InstNode in2 = InstructionsTree[INST_NODE_INDEX(in) + ((tmpIndex2 >> 3) & 7)]; + /* + * Do NOT check for NULL here, since we do a bit of a guess work, + * hence we don't override 'in', cause we might still need it. + */ + instType = INST_NODE_TYPE(in2); + + if (instType == INT_INFO) ii = &InstInfos[INST_NODE_INDEX(in2)]; + else if (instType == INT_INFOEX) ii = (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in2)]; + + /* + * OCST_2dBYTES is complex, because there are a few instructions which are not divided in some special cases. + * If the instruction wasn't divided (but still it must be a 2.3 because we are in divided category) + * or it was an official 2.3 (because its index was less than 0xc0) - + * Then it means the instruction should be using the REG bits, otherwise give a chance to range 0xc0-0xff. + */ + /* If we found an instruction only by its REG bits, AND it is not divided, then return it. */ + if ((ii != NULL) && (INST_INFO_FLAGS(ii) & INST_NOT_DIVIDED)) return ii; + /* Otherwise, if the range is above 0xc0, try the special divided range (range 0x8-0xc0 is omitted). */ + if (tmpIndex2 >= INST_DIVIDED_MODRM) return inst_get_info(in, tmpIndex2 - INST_DIVIDED_MODRM + 8); + + /* It might be that we got here without touching ii in the above if statements, then it becomes an invalid instruction prolly. */ + return ii; + } + + /* Try 3 full bytes (OCST_3BYTES - no ModRM byte). */ + if (instType == INT_LIST_FULL) { + /* OCST_3BYTES. */ + in = InstructionsTree[INST_NODE_INDEX(in) + tmpIndex2]; + if (in == INT_NOTEXISTS) return NULL; + instType = INST_NODE_TYPE(in); + + if (instType < INT_INFOS) + return instType == INT_INFO ? &InstInfos[INST_NODE_INDEX(in)] : (_InstInfo*)&InstInfosEx[INST_NODE_INDEX(in)]; + + if (instType == INT_LIST_PREFIXED) return inst_lookup_prefixed(in, ps); + } + + /* Kahtchinggg, damn. */ + return NULL; +} + +/* +* 3DNow! instruction handling: + +* This is used when we encounter a 3DNow! instruction. +* We can't really locate a 3DNow! instruction before we see two escaped bytes, +* 0x0f, 0x0f. Then we have to extract operands which are, dest=mmx register, src=mmx register or quadword indirection. +* When we are finished with the extraction of operands we can resume to locate the instruction by reading another byte +* which tells us which 3DNow instruction we really tracked down... +* So in order to tell the extract operands function which operands the 3DNow! instruction require, we need to set up some +* generic instruction info for 3DNow! instructions. + +* In the inst_lookup itself, when we read an OCST_3BYTES which the two first bytes are 0x0f and 0x0f. +* we will return this special generic II for the specific operands we are interested in (MM, MM64). +* Then after extracting the operand, we'll call a completion routine for locating the instruction +* which will be called only for 3DNow! instructions, distinguished by a flag, and it will read the last byte of the 3 bytes. +* +* The id of this opcode should not be used, the following function should change it anyway. +*/ +_InstInfo* inst_lookup_3dnow(_CodeInfo* ci) +{ + /* Start off from the two escape bytes gates... which is 3DNow! table.*/ + _InstNode in = Table_0F_0F; + + int index; + + /* Make sure we can read a byte off the stream. */ + if (ci->codeLen < 1) return NULL; + + index = *ci->code; + + ci->codeLen -= 1; + ci->code += 1; + return inst_get_info(in, index); +} diff --git a/source/distorm/instructions.h b/source/distorm/instructions.h new file mode 100644 index 0000000..b8d8a64 --- /dev/null +++ b/source/distorm/instructions.h @@ -0,0 +1,463 @@ +/* +instructions.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef INSTRUCTIONS_H +#define INSTRUCTIONS_H + +#include "config.h" +#include "prefix.h" + + +/* + * Operand type possibilities: + * Note "_FULL" suffix indicates to decode the operand as 16 bits or 32 bits depends on DecodeType - + * actually, it depends on the decoding mode, unless there's an operand/address size prefix. + * For example, the code: 33 c0 could be decoded/executed as XOR AX, AX or XOR EAX, EAX. + */ +typedef enum OpType { + /* No operand is set */ + OT_NONE = 0, + + /* Read a byte(8 bits) immediate */ + OT_IMM8, + /* Force a read of a word(16 bits) immediate, used by ret only */ + OT_IMM16, + /* Read a word/dword immediate */ + OT_IMM_FULL, + /* Read a double-word(32 bits) immediate */ + OT_IMM32, + + /* Read a signed extended byte(8 bits) immediate */ + OT_SEIMM8, + + /* + * Special immediates for instructions which have more than one immediate, + * which is an exception from standard instruction format. + * As to version v1.0: ENTER, INSERTQ, EXTRQ are the only problematic ones. + */ + /* 16 bits immediate using the first imm-slot */ + OT_IMM16_1, + /* 8 bits immediate using the first imm-slot */ + OT_IMM8_1, + /* 8 bits immediate using the second imm-slot */ + OT_IMM8_2, + + /* Use a 8bit register */ + OT_REG8, + /* Use a 16bit register */ + OT_REG16, + /* Use a 16/32/64bit register */ + OT_REG_FULL, + /* Use a 32bit register */ + OT_REG32, + /* + * If used with REX the reg operand size becomes 64 bits, otherwise 32 bits. + * VMX instructions are promoted automatically without a REX prefix. + */ + OT_REG32_64, + /* Used only by MOV CR/DR(n). Promoted with REX onlly. */ + OT_FREG32_64_RM, + + /* Use or read (indirection) a 8bit register or immediate byte */ + OT_RM8, + /* Some instructions force 16 bits (mov sreg, rm16) */ + OT_RM16, + /* Use or read a 16/32/64bit register or immediate word/dword/qword */ + OT_RM_FULL, + /* + * 32 or 64 bits (with REX) operand size indirection memory operand. + * Some instructions are promoted automatically without a REX prefix. + */ + OT_RM32_64, + /* 16 or 32 bits RM. This is used only with MOVZXD instruction in 64bits. */ + OT_RM16_32, + /* Same as OT_RMXX but POINTS to 16 bits [cannot use GENERAL-PURPOSE REG!] */ + OT_FPUM16, + /* Same as OT_RMXX but POINTS to 32 bits (single precision) [cannot use GENERAL-PURPOSE REG!] */ + OT_FPUM32, + /* Same as OT_RMXX but POINTS to 64 bits (double precision) [cannot use GENERAL-PURPOSE REG!] */ + OT_FPUM64, + /* Same as OT_RMXX but POINTS to 80 bits (extended precision) [cannot use GENERAL-PURPOSE REG!] */ + OT_FPUM80, + + /* + * Special operand type for SSE4 where the ModR/M might + * be a 32 bits register or 8 bits memory indirection operand. + */ + OT_R32_M8, + /* + * Special ModR/M for PINSRW, which need a 16 bits memory operand or 32 bits register. + * In 16 bits decoding mode R32 becomes R16, operand size cannot affect this. + */ + OT_R32_M16, + /* + * Special type for SSE4, ModR/M might be a 32 bits or 64 bits (with REX) register or + * a 8 bits memory indirection operand. + */ + OT_R32_64_M8, + /* + * Special type for SSE4, ModR/M might be a 32 bits or 64 bits (with REX) register or + * a 16 bits memory indirection operand. + */ + OT_R32_64_M16, + /* + * Special operand type for MOV reg16/32/64/mem16, segReg 8C /r. and SMSW. + * It supports all decoding modes, but if used as a memory indirection it's a 16 bit ModR/M indirection. + */ + OT_RFULL_M16, + + /* Use a control register */ + OT_CREG, + /* Use a debug register */ + OT_DREG, + /* Use a segment register */ + OT_SREG, + /* + * SEG is encoded in the flags of the opcode itself! + * This is used for specific "push SS" where SS is a segment where + * each "push SS" has an absolutely different opcode byte. + * We need this to detect whether an operand size prefix is used. + */ + OT_SEG, + + /* Use AL */ + OT_ACC8, + /* Use AX (FSTSW) */ + OT_ACC16, + /* Use AX/EAX/RAX */ + OT_ACC_FULL, + /* Use AX/EAX, no REX is possible for RAX, used only with IN/OUT which don't support 64 bit registers */ + OT_ACC_FULL_NOT64, + + /* + * Read one word (seg), and a word/dword/qword (depends on operand size) from memory. + * JMP FAR [EBX] means EBX point to 16:32 ptr. + */ + OT_MEM16_FULL, + /* Read one word (seg) and a word/dword/qword (depends on operand size), usually SEG:OFF, JMP 1234:1234 */ + OT_PTR16_FULL, + /* Read one word (limit) and a dword/qword (limit) (depends on operand size), used by SGDT, SIDT, LGDT, LIDT. */ + OT_MEM16_3264, + + /* Read a byte(8 bits) immediate and calculate it relatively to the current offset of the instruction being decoded */ + OT_RELCB, + /* Read a word/dword immediate and calculate it relatively to the current offset of the instruction being decoded */ + OT_RELC_FULL, + + /* Use general memory indirection, with varying sizes: */ + OT_MEM, + /* Used when a memory indirection is required, but if the mod field is 11, this operand will be ignored. */ + OT_MEM_OPT, + OT_MEM32, + /* Memory dereference for MOVNTI, either 32 or 64 bits (with REX). */ + OT_MEM32_64, + OT_MEM64, + OT_MEM128, + /* Used for cmpxchg8b/16b. */ + OT_MEM64_128, + + /* Read an immediate as an absolute address, size is known by instruction, used by MOV (memory offset) only */ + OT_MOFFS8, + OT_MOFFS_FULL, + /* Use an immediate of 1, as for SHR R/M, 1 */ + OT_CONST1, + /* Use CL, as for SHR R/M, CL */ + OT_REGCL, + + /* + * Instruction-Block for one byte long instructions, used by INC/DEC/PUSH/POP/XCHG, + * REG is extracted from the value of opcode + * Use a 8bit register + */ + OT_IB_RB, + /* Use a 16/32/64bit register */ + OT_IB_R_FULL, + + /* Use [(r)SI] as INDIRECTION, for repeatable instructions */ + OT_REGI_ESI, + /* Use [(r)DI] as INDIRECTION, for repeatable instructions */ + OT_REGI_EDI, + /* Use [(r)BX + AL] as INDIRECTIOM, used by XLAT only */ + OT_REGI_EBXAL, + /* Use [(r)AX] as INDIRECTION, used by AMD's SVM instructions */ + OT_REGI_EAX, + /* Use DX, as for OUTS DX, BYTE [SI] */ + OT_REGDX, + /* Use ECX in INVLPGA instruction */ + OT_REGECX, + + /* FPU registers: */ + OT_FPU_SI, /* ST(i) */ + OT_FPU_SSI, /* ST(0), ST(i) */ + OT_FPU_SIS, /* ST(i), ST(0) */ + + /* MMX registers: */ + OT_MM, + /* Extract the MMX register from the RM bits this time (used when the REG bits are used for opcode extension) */ + OT_MM_RM, + /* ModR/M points to 32 bits MMX variable */ + OT_MM32, + /* ModR/M points to 32 bits MMX variable */ + OT_MM64, + + /* SSE registers: */ + OT_XMM, + /* Extract the SSE register from the RM bits this time (used when the REG bits are used for opcode extension) */ + OT_XMM_RM, + /* ModR/M points to 16 bits SSE variable */ + OT_XMM16, + /* ModR/M points to 32 bits SSE variable */ + OT_XMM32, + /* ModR/M points to 64 bits SSE variable */ + OT_XMM64, + /* ModR/M points to 128 bits SSE variable */ + OT_XMM128, + /* Implied XMM0 register as operand, used in SSE4. */ + OT_REGXMM0, + + /* AVX operands: */ + + /* ModR/M for 32 bits. */ + OT_RM32, + /* Reg32/Reg64 (prefix width) or Mem8. */ + OT_REG32_64_M8, + /* Reg32/Reg64 (prefix width) or Mem16. */ + OT_REG32_64_M16, + /* Reg32/Reg 64 depends on prefix width only. */ + OT_WREG32_64, + /* RM32/RM64 depends on prefix width only. */ + OT_WRM32_64, + /* XMM or Mem32/Mem64 depends on perfix width only. */ + OT_WXMM32_64, + /* XMM is encoded in VEX.VVVV. */ + OT_VXMM, + /* XMM is encoded in the high nibble of an immediate byte. */ + OT_XMM_IMM, + /* YMM/XMM is dependent on VEX.L. */ + OT_YXMM, + /* YMM/XMM (depends on prefix length) is encoded in the high nibble of an immediate byte. */ + OT_YXMM_IMM, + /* YMM is encoded in reg. */ + OT_YMM, + /* YMM or Mem256. */ + OT_YMM256, + /* YMM is encoded in VEX.VVVV. */ + OT_VYMM, + /* YMM/XMM is dependent on VEX.L, and encoded in VEX.VVVV. */ + OT_VYXMM, + /* YMM/XMM or Mem64/Mem256 is dependent on VEX.L. */ + OT_YXMM64_256, + /* YMM/XMM or Mem128/Mem256 is dependent on VEX.L. */ + OT_YXMM128_256, + /* XMM or Mem64/Mem256 is dependent on VEX.L. */ + OT_LXMM64_128, + /* Mem128/Mem256 is dependent on VEX.L. */ + OT_LMEM128_256 +} _OpType; + +/* Flags for instruction: */ + +/* Empty flags indicator: */ +#define INST_FLAGS_NONE (0) +/* The instruction we are going to decode requires ModR/M encoding. */ +#define INST_MODRM_REQUIRED (1) +/* Special treatment for instructions which are in the divided-category but still needs the whole byte for ModR/M... */ +#define INST_NOT_DIVIDED (1 << 1) +/* + * Used explicitly in repeatable instructions, + * which needs a suffix letter in their mnemonic to specify operation-size (depend on operands). + */ +#define INST_16BITS (1 << 2) +/* If the opcode is supported by 80286 and upper models (16/32 bits). */ +#define INST_32BITS (1 << 3) +/* + * Prefix flags (6 types: lock/rep, seg override, addr-size, oper-size, REX, VEX) + * There are several specific instructions that can follow LOCK prefix, + * note that they must be using a memory operand form, otherwise they generate an exception. + */ +#define INST_PRE_LOCK (1 << 4) +/* REPNZ prefix for string instructions only - means an instruction can follow it. */ +#define INST_PRE_REPNZ (1 << 5) +/* REP prefix for string instructions only - means an instruction can follow it. */ +#define INST_PRE_REP (1 << 6) +/* CS override prefix. */ +#define INST_PRE_CS (1 << 7) +/* SS override prefix. */ +#define INST_PRE_SS (1 << 8) +/* DS override prefix. */ +#define INST_PRE_DS (1 << 9) +/* ES override prefix. */ +#define INST_PRE_ES (1 << 10) +/* FS override prefix. Funky Segment :) */ +#define INST_PRE_FS (1 << 11) +/* GS override prefix. Groovy Segment, of course not, duh ! */ +#define INST_PRE_GS (1 << 12) +/* Switch operand size from 32 to 16 and vice versa. */ +#define INST_PRE_OP_SIZE (1 << 13) +/* Switch address size from 32 to 16 and vice versa. */ +#define INST_PRE_ADDR_SIZE (1 << 14) +/* Native instructions which needs suffix letter to indicate their operation-size (and don't depend on operands). */ +#define INST_NATIVE (1 << 15) +/* Use extended mnemonic, means it's an _InstInfoEx structure, which contains another mnemonic for 32 bits specifically. */ +#define INST_USE_EXMNEMONIC (1 << 16) +/* Use third operand, means it's an _InstInfoEx structure, which contains another operand for special instructions. */ +#define INST_USE_OP3 (1 << 17) +/* Use fourth operand, means it's an _InstInfoEx structure, which contains another operand for special instructions. */ +#define INST_USE_OP4 (1 << 18) +/* The instruction's mnemonic depends on the mod value of the ModR/M byte (mod=11, mod!=11). */ +#define INST_MNEMONIC_MODRM_BASED (1 << 19) +/* The instruction uses a ModR/M byte which the MOD must be 11 (for registers operands only). */ +#define INST_MODRR_REQUIRED (1 << 20) +/* The way of 3DNow! instructions are built, we have to handle their locating specially. Suffix imm8 tells which instruction it is. */ +#define INST_3DNOW_FETCH (1 << 21) +/* The instruction needs two suffixes, one for the comparison type (imm8) and the second for its operation size indication (second mnemonic). */ +#define INST_PSEUDO_OPCODE (1 << 22) +/* Invalid instruction at 64 bits decoding mode. */ +#define INST_INVALID_64BITS (1 << 23) +/* Specific instruction can be promoted to 64 bits (without REX, it is promoted automatically). */ +#define INST_64BITS (1 << 24) +/* Indicates the instruction must be REX prefixed in order to use 64 bits operands. */ +#define INST_PRE_REX (1 << 25) +/* Third mnemonic is set. */ +#define INST_USE_EXMNEMONIC2 (1 << 26) +/* Instruction is only valid in 64 bits decoding mode. */ +#define INST_64BITS_FETCH (1 << 27) +/* Forces that the ModRM-REG/Opcode field will be 0. (For EXTRQ). */ +#define INST_FORCE_REG0 (1 << 28) +/* Indicates that instruction is encoded with a VEX prefix. */ +#define INST_PRE_VEX (1 << 29) +/* Indicates that the instruction is encoded with a ModRM byte (REG field specifically). */ +#define INST_MODRM_INCLUDED (1 << 30) +/* Indicates that the first (/destination) operand of the instruction is writable. */ +#define INST_DST_WR (1 << 31) + +#define INST_PRE_REPS (INST_PRE_REPNZ | INST_PRE_REP) +#define INST_PRE_LOKREP_MASK (INST_PRE_LOCK | INST_PRE_REPNZ | INST_PRE_REP) +#define INST_PRE_SEGOVRD_MASK32 (INST_PRE_CS | INST_PRE_SS | INST_PRE_DS | INST_PRE_ES) +#define INST_PRE_SEGOVRD_MASK64 (INST_PRE_FS | INST_PRE_GS) +#define INST_PRE_SEGOVRD_MASK (INST_PRE_SEGOVRD_MASK32 | INST_PRE_SEGOVRD_MASK64) + +/* Extended flags for VEX: */ +/* Indicates that the instruction might have VEX.L encoded. */ +#define INST_VEX_L (1) +/* Indicates that the instruction might have VEX.W encoded. */ +#define INST_VEX_W (1 << 1) +/* Indicates that the mnemonic of the instruction is based on the VEX.W bit. */ +#define INST_MNEMONIC_VEXW_BASED (1 << 2) +/* Indicates that the mnemonic of the instruction is based on the VEX.L bit. */ +#define INST_MNEMONIC_VEXL_BASED (1 << 3) +/* Forces the instruction to be encoded with VEX.L, otherwise it's undefined. */ +#define INST_FORCE_VEXL (1 << 4) +/* + * Indicates that the instruction is based on the MOD field of the ModRM byte. + * (MOD==11: got the right instruction, else skip +4 in prefixed table for the correct instruction). + */ +#define INST_MODRR_BASED (1 << 5) +/* Indicates that the instruction doesn't use the VVVV field of the VEX prefix, if it does then it's undecodable. */ +#define INST_VEX_V_UNUSED (1 << 6) + +/* Indication that the instruction is privileged (Ring 0), this should be checked on the opcodeId field. */ +#define OPCODE_ID_PRIVILEGED ((uint16_t)0x8000) + +/* + * Indicates which operand is being decoded. + * Destination (1st), Source (2nd), op3 (3rd), op4 (4th). + * Used to set the operands' fields in the _DInst structure! + */ +typedef enum {ONT_NONE = -1, ONT_1 = 0, ONT_2 = 1, ONT_3 = 2, ONT_4 = 3} _OperandNumberType; + +/* CPU Flags that instructions modify, test or undefine, in compacted form (CF,PF,AF,ZF,SF are 1:1 map to EFLAGS). */ +#define D_COMPACT_CF 1 /* Carry */ +#define D_COMPACT_PF 4 /* Parity */ +#define D_COMPACT_AF 0x10 /* Auxiliary */ +#define D_COMPACT_ZF 0x40 /* Zero */ +#define D_COMPACT_SF 0x80 /* Sign */ +/* The following flags have to be translated to EFLAGS. */ +#define D_COMPACT_IF 2 /* Interrupt */ +#define D_COMPACT_DF 8 /* Direction */ +#define D_COMPACT_OF 0x20 /* Overflow */ + +/* The mask of flags that are already compatible with EFLAGS. */ +#define D_COMPACT_SAME_FLAGS (D_COMPACT_CF | D_COMPACT_PF | D_COMPACT_AF | D_COMPACT_ZF | D_COMPACT_SF) + +/* + * In order to save more space for storing the DB statically, + * I came up with another level of shared info. + * Because I saw that most of the information that instructions use repeats itself. + * + * Info about the instruction, source/dest types, meta and flags. + * _InstInfo points to a table of _InstSharedInfo. + */ +typedef struct { + uint8_t flagsIndex; /* An index into FlagsTables */ + uint8_t s, d; /* OpType. */ + uint8_t meta; /* Hi 5 bits = Instruction set class | Lo 3 bits = flow control flags. */ + /* + * The following are CPU flag masks that the instruction changes. + * The flags are compacted so 8 bits representation is enough. + * They will be expanded in runtime to be compatible to EFLAGS. + */ + uint8_t modifiedFlagsMask; + uint8_t testedFlagsMask; + uint8_t undefinedFlagsMask; +} _InstSharedInfo; + +/* + * This structure is used for the instructions DB and NOT for the disassembled result code! + * This is the BASE structure, there are extensions to this structure below. + */ +typedef struct { + uint16_t sharedIndex; /* An index into the SharedInfoTable. */ + uint16_t opcodeId; /* The opcodeId is really a byte-offset into the mnemonics table. MSB is a privileged indication. */ +} _InstInfo; + +/* + * There are merely few instructions which need a second mnemonic for 32 bits. + * Or a third for 64 bits. Therefore sometimes the second mnemonic is empty but not the third. + * In all decoding modes the first mnemonic is the default. + * A flag will indicate it uses another mnemonic. + * + * There are a couple of (SSE4) instructions in the whole DB which need both op3 and 3rd mnemonic for 64bits, + * therefore, I decided to make the extended structure contain all extra info in the same structure. + * There are a few instructions (SHLD/SHRD/IMUL and SSE too) which use third operand (or a fourth). + * A flag will indicate it uses a third/fourth operand. + */ +typedef struct { + /* Base structure (doesn't get accessed directly from code). */ + _InstInfo BASE; + + /* Extended starts here. */ + uint8_t flagsEx; /* 8 bits are enough, in the future we might make it a bigger integer. */ + uint8_t op3, op4; /* OpType. */ + uint16_t opcodeId2, opcodeId3; +} _InstInfoEx; + +/* Trie data structure node type: */ +typedef enum { + INT_NOTEXISTS = 0, /* Not exists. */ + INT_INFO = 1, /* It's an instruction info. */ + INT_INFOEX, + INT_LIST_GROUP, + INT_LIST_FULL, + INT_LIST_DIVIDED, + INT_LIST_PREFIXED +} _InstNodeType; + +/* Used to check instType < INT_INFOS, means we got an inst-info. Cause it has to be only one of them. */ +#define INT_INFOS (INT_LIST_GROUP) + +/* Instruction node is treated as { int index:13; int type:3; } */ +typedef uint16_t _InstNode; + +_InstInfo* inst_lookup(_CodeInfo* ci, _PrefixState* ps); +_InstInfo* inst_lookup_3dnow(_CodeInfo* ci); + +#endif /* INSTRUCTIONS_H */ diff --git a/source/distorm/insts.c b/source/distorm/insts.c new file mode 100644 index 0000000..a081a2d --- /dev/null +++ b/source/distorm/insts.c @@ -0,0 +1,7939 @@ +/* +insts.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "config.h" +#include "insts.h" +#include "instructions.h" + + +/* +* GENERATED BY disOps at Sun Jul 09 21:22:14 2017 +*/ + +_InstInfo II_MOVSXD = /*II*/{ 0x1d3, 10027 }; +_InstInfo II_NOP = /*II*/{ 0x53, 581 }; +_InstInfo II_PAUSE = /*II*/{ 0x88, 10035 }; +_InstInfo II_WAIT = /*II*/{ 0x53, 10042 }; +_InstInfo II_RDRAND = /*II*/{ 0x1d4, 10048 }; +_InstInfo II_3DNOW = /*II*/{ 0x1d5, 10056 }; + +_iflags FlagsTable[101] = { + 0x80000011, + 0x80000000, + 0x800400, + 0x80800400, + 0x800080, + 0x800100, + 0x80800100, + 0x800200, + 0x80800200, + 0x800000, + 0x1, + 0x0, + 0x80800000, + 0x1000000, + 0x81000000, + 0x808000, + 0x800001, + 0x80020001, + 0x1002000, + 0x60, + 0x64, + 0x80000001, + 0x4010000, + 0x1008000, + 0x80000060, + 0x83000064, + 0x3000064, + 0x83000000, + 0x3008000, + 0x200, + 0xc000, + 0x4014000, + 0x8, + 0x81000009, + 0x9, + 0x80000009, + 0x1000808, + 0x81000808, + 0x80020009, + 0x1001008, + 0x81001008, + 0x80000019, + 0x3000009, + 0x83000009, + 0x83000008, + 0xc0000011, + 0x40000001, + 0xc0800011, + 0x40800001, + 0xc0000019, + 0xc1000001, + 0xc0000001, + 0xc0000003, + 0x41000000, + 0x40000000, + 0x40000008, + 0x40000009, + 0x41000001, + 0x43000001, + 0x40000003, + 0x48000000, + 0x200009, + 0x20000009, + 0x60020009, + 0x60000009, + 0x80090009, + 0x200b0009, + 0x20020009, + 0x80100009, + 0x21100009, + 0x87000009, + 0x20009, + 0x20000008, + 0x1000009, + 0x10020009, + 0x160009, + 0x100009, + 0x47000009, + 0x47090009, + 0x40090009, + 0x80002009, + 0xc0000009, + 0x2001, + 0x80002001, + 0x410009, + 0x20420009, + 0x20060009, + 0x120009, + 0x21020009, + 0xc7000019, + 0x20100009, + 0xc0002009, + 0x40002008, + 0xc0000000, + 0xc0002008, + 0x4020009, + 0x40100009, + 0x60120009, + 0x41000009, + 0x83000001, + 0x200001 +}; + +_InstNode Table_0F = 256; +_InstNode Table_0F_0F = 1440; +_InstNode Table_0F_38 = 1896; +_InstNode Table_0F_3A = 2152; + +_InstInfo InstInfos[1246] = { + /*II_00*/{ 0x0, 11 }, + /*II_01*/{ 0x1, 11 }, + /*II_02*/{ 0x2, 11 }, + /*II_03*/{ 0x3, 11 }, + /*II_04*/{ 0x4, 11 }, + /*II_05*/{ 0x5, 11 }, + /*II_06*/{ 0x6, 16 }, + /*II_07*/{ 0x7, 22 }, + /*II_08*/{ 0x8, 27 }, + /*II_09*/{ 0x9, 27 }, + /*II_0A*/{ 0xa, 27 }, + /*II_0B*/{ 0xb, 27 }, + /*II_0C*/{ 0xc, 27 }, + /*II_0D*/{ 0xd, 27 }, + /*II_0E*/{ 0xe, 16 }, + /*II_10*/{ 0xf, 31 }, + /*II_11*/{ 0x10, 31 }, + /*II_12*/{ 0x11, 31 }, + /*II_13*/{ 0x12, 31 }, + /*II_14*/{ 0x13, 31 }, + /*II_15*/{ 0x14, 31 }, + /*II_16*/{ 0x15, 16 }, + /*II_17*/{ 0x16, 22 }, + /*II_18*/{ 0xf, 36 }, + /*II_19*/{ 0x10, 36 }, + /*II_1A*/{ 0x11, 36 }, + /*II_1B*/{ 0x12, 36 }, + /*II_1C*/{ 0x13, 36 }, + /*II_1D*/{ 0x14, 36 }, + /*II_1E*/{ 0x17, 16 }, + /*II_1F*/{ 0x18, 22 }, + /*II_20*/{ 0x19, 41 }, + /*II_21*/{ 0x1a, 41 }, + /*II_22*/{ 0x1b, 41 }, + /*II_23*/{ 0x1c, 41 }, + /*II_24*/{ 0x1d, 41 }, + /*II_25*/{ 0x1e, 41 }, + /*II_27*/{ 0x1f, 46 }, + /*II_28*/{ 0x0, 51 }, + /*II_29*/{ 0x1, 51 }, + /*II_2A*/{ 0x2, 51 }, + /*II_2B*/{ 0x3, 51 }, + /*II_2C*/{ 0x4, 51 }, + /*II_2D*/{ 0x5, 51 }, + /*II_2F*/{ 0x1f, 56 }, + /*II_30*/{ 0x20, 61 }, + /*II_31*/{ 0x21, 61 }, + /*II_32*/{ 0x22, 61 }, + /*II_33*/{ 0x23, 61 }, + /*II_34*/{ 0x24, 61 }, + /*II_35*/{ 0x25, 61 }, + /*II_37*/{ 0x26, 66 }, + /*II_38*/{ 0x27, 71 }, + /*II_39*/{ 0x28, 71 }, + /*II_3A*/{ 0x29, 71 }, + /*II_3B*/{ 0x2a, 71 }, + /*II_3C*/{ 0x2b, 71 }, + /*II_3D*/{ 0x2c, 71 }, + /*II_3F*/{ 0x26, 76 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_40*/{ 0x2d, 81 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_48*/{ 0x2d, 86 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_50*/{ 0x2e, 16 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_58*/{ 0x2f, 22 }, + /*II_60*/{ 0x30, 91 }, + /*II_61*/{ 0x30, 98 }, + /*II_62*/{ 0x31, 104 }, + /*II_63*/{ 0x32, 111 }, + /*II_68*/{ 0x33, 16 }, + /*II_6A*/{ 0x35, 16 }, + /*II_6C*/{ 0x36, 32891 }, + /*II_6D*/{ 0x37, 32891 }, + /*II_6E*/{ 0x38, 32896 }, + /*II_6F*/{ 0x39, 32896 }, + /*II_70*/{ 0x3a, 134 }, + /*II_71*/{ 0x3a, 138 }, + /*II_72*/{ 0x3b, 143 }, + /*II_73*/{ 0x3b, 147 }, + /*II_74*/{ 0x3c, 152 }, + /*II_75*/{ 0x3c, 156 }, + /*II_76*/{ 0x3d, 161 }, + /*II_77*/{ 0x3d, 166 }, + /*II_78*/{ 0x3e, 170 }, + /*II_79*/{ 0x3e, 174 }, + /*II_7A*/{ 0x3f, 179 }, + /*II_7B*/{ 0x3f, 183 }, + /*II_7C*/{ 0x40, 188 }, + /*II_7D*/{ 0x40, 192 }, + /*II_7E*/{ 0x41, 197 }, + /*II_7F*/{ 0x41, 202 }, + /*II_84*/{ 0x42, 206 }, + /*II_85*/{ 0x43, 206 }, + /*II_86*/{ 0x44, 212 }, + /*II_87*/{ 0x45, 212 }, + /*II_88*/{ 0x46, 218 }, + /*II_89*/{ 0x47, 218 }, + /*II_8A*/{ 0x48, 218 }, + /*II_8B*/{ 0x49, 218 }, + /*II_8C*/{ 0x4a, 218 }, + /*II_8D*/{ 0x4b, 223 }, + /*II_8E*/{ 0x4c, 218 }, + /*II_90*/{ 0x4d, 212 }, + /*II_91*/{ 0x4d, 212 }, + /*II_92*/{ 0x4d, 212 }, + /*II_93*/{ 0x4d, 212 }, + /*II_94*/{ 0x4d, 212 }, + /*II_95*/{ 0x4d, 212 }, + /*II_96*/{ 0x4d, 212 }, + /*II_97*/{ 0x4d, 212 }, + /*II_9A*/{ 0x4f, 260 }, + /*II_9C*/{ 0x50, 270 }, + /*II_9D*/{ 0x51, 277 }, + /*II_9E*/{ 0x52, 283 }, + /*II_9F*/{ 0x53, 289 }, + /*II_A0*/{ 0x54, 218 }, + /*II_A1*/{ 0x55, 218 }, + /*II_A2*/{ 0x56, 218 }, + /*II_A3*/{ 0x57, 218 }, + /*II_A4*/{ 0x58, 295 }, + /*II_A5*/{ 0x59, 295 }, + /*II_A6*/{ 0x5a, 301 }, + /*II_A7*/{ 0x5b, 301 }, + /*II_A8*/{ 0x5c, 206 }, + /*II_A9*/{ 0x5d, 206 }, + /*II_AA*/{ 0x5e, 307 }, + /*II_AB*/{ 0x5f, 307 }, + /*II_AC*/{ 0x60, 313 }, + /*II_AD*/{ 0x61, 313 }, + /*II_AE*/{ 0x62, 319 }, + /*II_AF*/{ 0x63, 319 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B0*/{ 0x64, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_B8*/{ 0x65, 218 }, + /*II_C2*/{ 0x66, 325 }, + /*II_C3*/{ 0x67, 325 }, + /*II_C4*/{ 0x68, 330 }, + /*II_C5*/{ 0x68, 335 }, + /*II_C8*/{ 0x69, 340 }, + /*II_C9*/{ 0x6a, 347 }, + /*II_CA*/{ 0x6b, 354 }, + /*II_CB*/{ 0x6c, 354 }, + /*II_CC*/{ 0x6d, 360 }, + /*II_CD*/{ 0x6e, 367 }, + /*II_CE*/{ 0x6f, 372 }, + /*II_CF*/{ 0x70, 33146 }, + /*II_D4*/{ 0x71, 384 }, + /*II_D5*/{ 0x71, 389 }, + /*II_D6*/{ 0x72, 394 }, + /*II_D7*/{ 0x73, 400 }, + /*II_E0*/{ 0x74, 406 }, + /*II_E1*/{ 0x74, 414 }, + /*II_E2*/{ 0x75, 421 }, + /*II_E4*/{ 0x77, 33215 }, + /*II_E5*/{ 0x78, 33215 }, + /*II_E6*/{ 0x79, 33219 }, + /*II_E7*/{ 0x7a, 33219 }, + /*II_E8*/{ 0x7b, 456 }, + /*II_E9*/{ 0x7c, 462 }, + /*II_EA*/{ 0x7d, 467 }, + /*II_EB*/{ 0x7e, 462 }, + /*II_EC*/{ 0x7f, 33215 }, + /*II_ED*/{ 0x80, 33215 }, + /*II_EE*/{ 0x81, 33219 }, + /*II_EF*/{ 0x82, 33219 }, + /*II_F1*/{ 0x6d, 476 }, + /*II_F4*/{ 0x53, 33250 }, + /*II_F5*/{ 0x83, 487 }, + /*II_F8*/{ 0x83, 492 }, + /*II_F9*/{ 0x83, 497 }, + /*II_FA*/{ 0x84, 33270 }, + /*II_FB*/{ 0x84, 33275 }, + /*II_FC*/{ 0x85, 512 }, + /*II_FD*/{ 0x85, 517 }, + /*II_0F_02*/{ 0x86, 522 }, + /*II_0F_03*/{ 0x86, 527 }, + /*II_0F_05*/{ 0x87, 532 }, + /*II_0F_06*/{ 0x88, 33309 }, + /*II_0F_07*/{ 0x87, 547 }, + /*II_0F_08*/{ 0x88, 33323 }, + /*II_0F_09*/{ 0x88, 33329 }, + /*II_0F_0B*/{ 0x89, 569 }, + /*II_0F_0E*/{ 0x8a, 574 }, + /*II_0F_1F*/{ 0x8b, 581 }, + /*II_0F_20*/{ 0x8c, 32986 }, + /*II_0F_21*/{ 0x8d, 32986 }, + /*II_0F_22*/{ 0x8e, 32986 }, + /*II_0F_23*/{ 0x8f, 32986 }, + /*II_0F_30*/{ 0x88, 33354 }, + /*II_0F_31*/{ 0x88, 33361 }, + /*II_0F_32*/{ 0x88, 33368 }, + /*II_0F_33*/{ 0x88, 33375 }, + /*II_0F_34*/{ 0x87, 614 }, + /*II_0F_35*/{ 0x87, 624 }, + /*II_0F_37*/{ 0x90, 633 }, + /*II_0F_40*/{ 0x91, 641 }, + /*II_0F_41*/{ 0x91, 648 }, + /*II_0F_42*/{ 0x92, 656 }, + /*II_0F_43*/{ 0x92, 663 }, + /*II_0F_44*/{ 0x93, 671 }, + /*II_0F_45*/{ 0x93, 678 }, + /*II_0F_46*/{ 0x94, 686 }, + /*II_0F_47*/{ 0x94, 694 }, + /*II_0F_48*/{ 0x95, 701 }, + /*II_0F_49*/{ 0x95, 708 }, + /*II_0F_4A*/{ 0x96, 716 }, + /*II_0F_4B*/{ 0x96, 723 }, + /*II_0F_4C*/{ 0x97, 731 }, + /*II_0F_4D*/{ 0x97, 738 }, + /*II_0F_4E*/{ 0x98, 746 }, + /*II_0F_4F*/{ 0x98, 754 }, + /*II_0F_80*/{ 0x99, 134 }, + /*II_0F_81*/{ 0x99, 138 }, + /*II_0F_82*/{ 0x9a, 143 }, + /*II_0F_83*/{ 0x9a, 147 }, + /*II_0F_84*/{ 0x9b, 152 }, + /*II_0F_85*/{ 0x9b, 156 }, + /*II_0F_86*/{ 0x9c, 161 }, + /*II_0F_87*/{ 0x9c, 166 }, + /*II_0F_88*/{ 0x9d, 170 }, + /*II_0F_89*/{ 0x9d, 174 }, + /*II_0F_8A*/{ 0x9e, 179 }, + /*II_0F_8B*/{ 0x9e, 183 }, + /*II_0F_8C*/{ 0x9f, 188 }, + /*II_0F_8D*/{ 0x9f, 192 }, + /*II_0F_8E*/{ 0xa0, 197 }, + /*II_0F_8F*/{ 0xa0, 202 }, + /*II_0F_90*/{ 0xa1, 761 }, + /*II_0F_91*/{ 0xa1, 767 }, + /*II_0F_92*/{ 0xa2, 774 }, + /*II_0F_93*/{ 0xa2, 780 }, + /*II_0F_94*/{ 0xa3, 787 }, + /*II_0F_95*/{ 0xa3, 793 }, + /*II_0F_96*/{ 0xa4, 800 }, + /*II_0F_97*/{ 0xa4, 807 }, + /*II_0F_98*/{ 0xa5, 813 }, + /*II_0F_99*/{ 0xa5, 819 }, + /*II_0F_9A*/{ 0xa6, 826 }, + /*II_0F_9B*/{ 0xa6, 832 }, + /*II_0F_9C*/{ 0xa7, 839 }, + /*II_0F_9D*/{ 0xa7, 845 }, + /*II_0F_9E*/{ 0xa8, 852 }, + /*II_0F_9F*/{ 0xa8, 859 }, + /*II_0F_A0*/{ 0xa9, 16 }, + /*II_0F_A1*/{ 0xaa, 22 }, + /*II_0F_A2*/{ 0x88, 865 }, + /*II_0F_A3*/{ 0xab, 872 }, + /*II_0F_A8*/{ 0xad, 16 }, + /*II_0F_A9*/{ 0xae, 22 }, + /*II_0F_AA*/{ 0xaf, 882 }, + /*II_0F_AB*/{ 0xb0, 887 }, + /*II_0F_AF*/{ 0xb1, 117 }, + /*II_0F_B0*/{ 0xb2, 898 }, + /*II_0F_B1*/{ 0xb3, 898 }, + /*II_0F_B2*/{ 0xb4, 907 }, + /*II_0F_B3*/{ 0xb0, 912 }, + /*II_0F_B4*/{ 0xb4, 917 }, + /*II_0F_B5*/{ 0xb4, 922 }, + /*II_0F_B6*/{ 0xb5, 927 }, + /*II_0F_B7*/{ 0xb6, 927 }, + /*II_0F_B9*/{ 0x89, 569 }, + /*II_0F_BB*/{ 0xb0, 934 }, + /*II_0F_BE*/{ 0xb5, 939 }, + /*II_0F_BF*/{ 0xb6, 939 }, + /*II_0F_C0*/{ 0xb2, 946 }, + /*II_0F_C1*/{ 0xb3, 946 }, + /*II_0F_C3*/{ 0xb7, 952 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_0F_C8*/{ 0xb8, 960 }, + /*II_80_00*/{ 0xb9, 11 }, + /*II_80_01*/{ 0xba, 27 }, + /*II_80_02*/{ 0xbb, 31 }, + /*II_80_03*/{ 0xbb, 36 }, + /*II_80_04*/{ 0xbc, 41 }, + /*II_80_05*/{ 0xb9, 51 }, + /*II_80_06*/{ 0xbd, 61 }, + /*II_80_07*/{ 0xbe, 71 }, + /*II_81_00*/{ 0xbf, 11 }, + /*II_81_01*/{ 0xc0, 27 }, + /*II_81_02*/{ 0xc1, 31 }, + /*II_81_03*/{ 0xc1, 36 }, + /*II_81_04*/{ 0xc2, 41 }, + /*II_81_05*/{ 0xbf, 51 }, + /*II_81_06*/{ 0xc3, 61 }, + /*II_81_07*/{ 0xc4, 71 }, + /*II_82_00*/{ 0xc5, 11 }, + /*II_82_01*/{ 0xc6, 27 }, + /*II_82_02*/{ 0xc7, 31 }, + /*II_82_03*/{ 0xc7, 36 }, + /*II_82_04*/{ 0xc8, 41 }, + /*II_82_05*/{ 0xc5, 51 }, + /*II_82_06*/{ 0xc9, 61 }, + /*II_82_07*/{ 0xca, 71 }, + /*II_83_00*/{ 0xcb, 11 }, + /*II_83_01*/{ 0xcc, 27 }, + /*II_83_02*/{ 0xcd, 31 }, + /*II_83_03*/{ 0xcd, 36 }, + /*II_83_04*/{ 0xce, 41 }, + /*II_83_05*/{ 0xcb, 51 }, + /*II_83_06*/{ 0xcf, 61 }, + /*II_83_07*/{ 0xd0, 71 }, + /*II_8F_00*/{ 0xd1, 22 }, + /*II_C0_00*/{ 0xd2, 967 }, + /*II_C0_01*/{ 0xd2, 972 }, + /*II_C0_02*/{ 0xd3, 977 }, + /*II_C0_03*/{ 0xd3, 982 }, + /*II_C0_04*/{ 0xd4, 987 }, + /*II_C0_05*/{ 0xd4, 992 }, + /*II_C0_06*/{ 0xd4, 997 }, + /*II_C0_07*/{ 0xd4, 1002 }, + /*II_C1_00*/{ 0xd5, 967 }, + /*II_C1_01*/{ 0xd5, 972 }, + /*II_C1_02*/{ 0xd6, 977 }, + /*II_C1_03*/{ 0xd6, 982 }, + /*II_C1_04*/{ 0xd7, 987 }, + /*II_C1_05*/{ 0xd7, 992 }, + /*II_C1_06*/{ 0xd7, 997 }, + /*II_C1_07*/{ 0xd7, 1002 }, + /*II_C6_00*/{ 0xd8, 218 }, + /*II_C6_F8*/{ 0xd9, 1007 }, + /*II_C7_00*/{ 0xda, 218 }, + /*II_C7_F8*/{ 0xdb, 1015 }, + /*II_D0_00*/{ 0xdc, 967 }, + /*II_D0_01*/{ 0xdc, 972 }, + /*II_D0_02*/{ 0xdd, 977 }, + /*II_D0_03*/{ 0xdd, 982 }, + /*II_D0_04*/{ 0xde, 987 }, + /*II_D0_05*/{ 0xde, 992 }, + /*II_D0_06*/{ 0xde, 997 }, + /*II_D0_07*/{ 0xde, 1002 }, + /*II_D1_00*/{ 0xdf, 967 }, + /*II_D1_01*/{ 0xdf, 972 }, + /*II_D1_02*/{ 0xe0, 977 }, + /*II_D1_03*/{ 0xe0, 982 }, + /*II_D1_04*/{ 0xe1, 987 }, + /*II_D1_05*/{ 0xe1, 992 }, + /*II_D1_06*/{ 0xe1, 997 }, + /*II_D1_07*/{ 0xe1, 1002 }, + /*II_D2_00*/{ 0xe2, 967 }, + /*II_D2_01*/{ 0xe2, 972 }, + /*II_D2_02*/{ 0xe3, 977 }, + /*II_D2_03*/{ 0xe3, 982 }, + /*II_D2_04*/{ 0xe4, 987 }, + /*II_D2_05*/{ 0xe4, 992 }, + /*II_D2_06*/{ 0xe4, 997 }, + /*II_D2_07*/{ 0xe4, 1002 }, + /*II_D3_00*/{ 0xe5, 967 }, + /*II_D3_01*/{ 0xe5, 972 }, + /*II_D3_02*/{ 0xe6, 977 }, + /*II_D3_03*/{ 0xe6, 982 }, + /*II_D3_04*/{ 0xe7, 987 }, + /*II_D3_05*/{ 0xe7, 992 }, + /*II_D3_06*/{ 0xe7, 997 }, + /*II_D3_07*/{ 0xe7, 1002 }, + /*II_D8_00*/{ 0xe8, 1023 }, + /*II_D8_01*/{ 0xe8, 1029 }, + /*II_D8_02*/{ 0xe8, 1035 }, + /*II_D8_03*/{ 0xe8, 1041 }, + /*II_D8_04*/{ 0xe8, 1048 }, + /*II_D8_05*/{ 0xe8, 1054 }, + /*II_D8_06*/{ 0xe8, 1061 }, + /*II_D8_07*/{ 0xe8, 1067 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C0*/{ 0xe9, 1023 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_C8*/{ 0xe9, 1029 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D0*/{ 0xea, 1035 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D9*/{ 0xeb, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_D8*/{ 0xea, 1041 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E0*/{ 0xe9, 1048 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_E8*/{ 0xe9, 1054 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F0*/{ 0xe9, 1061 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D8_F8*/{ 0xe9, 1067 }, + /*II_D9_00*/{ 0xe8, 1074 }, + /*II_D9_02*/{ 0xec, 1079 }, + /*II_D9_03*/{ 0xec, 1084 }, + /*II_D9_04*/{ 0xed, 1090 }, + /*II_D9_05*/{ 0xee, 1098 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C0*/{ 0xea, 1074 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C9*/{ 0xeb, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_C8*/{ 0xea, 1105 }, + /*II_D9_D0*/{ 0xeb, 1111 }, + /*II_D9_E0*/{ 0xeb, 1117 }, + /*II_D9_E1*/{ 0xeb, 1123 }, + /*II_D9_E4*/{ 0xeb, 1129 }, + /*II_D9_E5*/{ 0xeb, 1135 }, + /*II_D9_E8*/{ 0xeb, 1141 }, + /*II_D9_E9*/{ 0xeb, 1147 }, + /*II_D9_EA*/{ 0xeb, 1155 }, + /*II_D9_EB*/{ 0xeb, 1163 }, + /*II_D9_EC*/{ 0xeb, 1170 }, + /*II_D9_ED*/{ 0xeb, 1178 }, + /*II_D9_EE*/{ 0xeb, 1186 }, + /*II_D9_F0*/{ 0xeb, 1192 }, + /*II_D9_F1*/{ 0xeb, 1199 }, + /*II_D9_F2*/{ 0xeb, 1206 }, + /*II_D9_F3*/{ 0xeb, 1213 }, + /*II_D9_F4*/{ 0xeb, 1221 }, + /*II_D9_F5*/{ 0xeb, 1230 }, + /*II_D9_F6*/{ 0xeb, 1238 }, + /*II_D9_F7*/{ 0xeb, 1247 }, + /*II_D9_F8*/{ 0xeb, 1256 }, + /*II_D9_F9*/{ 0xeb, 1263 }, + /*II_D9_FA*/{ 0xeb, 1272 }, + /*II_D9_FB*/{ 0xeb, 1279 }, + /*II_D9_FC*/{ 0xeb, 1288 }, + /*II_D9_FD*/{ 0xeb, 1297 }, + /*II_D9_FE*/{ 0xeb, 1305 }, + /*II_D9_FF*/{ 0xeb, 1311 }, + /*II_DA_00*/{ 0xe8, 1317 }, + /*II_DA_01*/{ 0xe8, 1324 }, + /*II_DA_02*/{ 0xe8, 1331 }, + /*II_DA_03*/{ 0xe8, 1338 }, + /*II_DA_04*/{ 0xe8, 1346 }, + /*II_DA_05*/{ 0xe8, 1353 }, + /*II_DA_06*/{ 0xe8, 1361 }, + /*II_DA_07*/{ 0xe8, 1368 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C0*/{ 0xef, 1376 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_C8*/{ 0xf0, 1384 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D0*/{ 0xf1, 1392 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_D8*/{ 0xf2, 1401 }, + /*II_DA_E9*/{ 0xeb, 1409 }, + /*II_DB_00*/{ 0xe8, 1418 }, + /*II_DB_01*/{ 0xf3, 1424 }, + /*II_DB_02*/{ 0xec, 1432 }, + /*II_DB_03*/{ 0xec, 1438 }, + /*II_DB_05*/{ 0xf4, 1074 }, + /*II_DB_07*/{ 0xf5, 1084 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C0*/{ 0xef, 1445 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_C8*/{ 0xf0, 1454 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D0*/{ 0xf1, 1463 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_D8*/{ 0xf2, 1473 }, + /*II_DB_E0*/{ 0xeb, 1482 }, + /*II_DB_E1*/{ 0xeb, 1488 }, + /*II_DB_E4*/{ 0xeb, 1496 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_E8*/{ 0xf6, 1504 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DB_F0*/{ 0xf7, 1512 }, + /*II_DC_00*/{ 0xf8, 1023 }, + /*II_DC_01*/{ 0xf8, 1029 }, + /*II_DC_02*/{ 0xf8, 1035 }, + /*II_DC_03*/{ 0xf8, 1041 }, + /*II_DC_04*/{ 0xf8, 1048 }, + /*II_DC_05*/{ 0xf8, 1054 }, + /*II_DC_06*/{ 0xf8, 1061 }, + /*II_DC_07*/{ 0xf8, 1067 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C0*/{ 0xf9, 1023 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_C8*/{ 0xf9, 1029 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E0*/{ 0xf9, 1054 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_E8*/{ 0xf9, 1048 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F0*/{ 0xf9, 1067 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DC_F8*/{ 0xf9, 1061 }, + /*II_DD_00*/{ 0xf8, 1074 }, + /*II_DD_01*/{ 0xfa, 1424 }, + /*II_DD_02*/{ 0xfb, 1079 }, + /*II_DD_03*/{ 0xfb, 1084 }, + /*II_DD_04*/{ 0xed, 1519 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_C0*/{ 0xea, 1527 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D0*/{ 0xea, 1079 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_D8*/{ 0xea, 1084 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E1*/{ 0xeb, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E0*/{ 0xf9, 1534 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E9*/{ 0xeb, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DD_E8*/{ 0xea, 1541 }, + /*II_DE_00*/{ 0xee, 1317 }, + /*II_DE_01*/{ 0xee, 1324 }, + /*II_DE_02*/{ 0xee, 1331 }, + /*II_DE_03*/{ 0xee, 1338 }, + /*II_DE_04*/{ 0xee, 1346 }, + /*II_DE_05*/{ 0xee, 1353 }, + /*II_DE_06*/{ 0xee, 1361 }, + /*II_DE_07*/{ 0xee, 1368 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C1*/{ 0xeb, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C0*/{ 0xf9, 1549 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C9*/{ 0xeb, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_C8*/{ 0xf9, 1556 }, + /*II_DE_D9*/{ 0xeb, 1563 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E1*/{ 0xeb, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E0*/{ 0xf9, 1571 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E9*/{ 0xeb, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_E8*/{ 0xf9, 1579 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F1*/{ 0xeb, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F0*/{ 0xf9, 1586 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F9*/{ 0xeb, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DE_F8*/{ 0xf9, 1594 }, + /*II_DF_00*/{ 0xee, 1418 }, + /*II_DF_01*/{ 0xfc, 1424 }, + /*II_DF_02*/{ 0xfd, 1432 }, + /*II_DF_03*/{ 0xfd, 1438 }, + /*II_DF_04*/{ 0xf4, 1601 }, + /*II_DF_05*/{ 0xf8, 1418 }, + /*II_DF_06*/{ 0xf5, 1607 }, + /*II_DF_07*/{ 0xfb, 1438 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_E8*/{ 0xf6, 1614 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_DF_F0*/{ 0xf6, 1623 }, + /*II_F6_00*/{ 0xfe, 206 }, + /*II_F6_02*/{ 0xff, 1631 }, + /*II_F6_03*/{ 0x100, 1636 }, + /*II_F6_04*/{ 0x101, 1641 }, + /*II_F6_05*/{ 0x101, 117 }, + /*II_F6_06*/{ 0x102, 1646 }, + /*II_F6_07*/{ 0x102, 1651 }, + /*II_F7_00*/{ 0x103, 206 }, + /*II_F7_02*/{ 0x104, 1631 }, + /*II_F7_03*/{ 0x105, 1636 }, + /*II_F7_04*/{ 0x106, 1641 }, + /*II_F7_05*/{ 0x106, 117 }, + /*II_F7_06*/{ 0x107, 1646 }, + /*II_F7_07*/{ 0x107, 1651 }, + /*II_FE_00*/{ 0x108, 81 }, + /*II_FE_01*/{ 0x108, 86 }, + /*II_FF_00*/{ 0x109, 81 }, + /*II_FF_01*/{ 0x109, 86 }, + /*II_FF_02*/{ 0x10a, 456 }, + /*II_FF_03*/{ 0x10b, 260 }, + /*II_FF_04*/{ 0x10c, 462 }, + /*II_FF_05*/{ 0x10d, 467 }, + /*II_FF_06*/{ 0x10e, 16 }, + /*II_0F_00_00*/{ 0x10f, 1657 }, + /*II_0F_00_01*/{ 0x110, 1663 }, + /*II_0F_00_02*/{ 0x110, 34436 }, + /*II_0F_00_03*/{ 0x111, 34442 }, + /*II_0F_00_04*/{ 0x112, 1679 }, + /*II_0F_00_05*/{ 0x112, 1685 }, + /*II_0F_01_00*/{ 0x113, 1691 }, + /*II_0F_01_01*/{ 0x113, 1697 }, + /*II_0F_01_02*/{ 0x113, 34471 }, + /*II_0F_01_03*/{ 0x113, 34477 }, + /*II_0F_01_04*/{ 0x114, 1715 }, + /*II_0F_01_06*/{ 0x115, 34489 }, + /*II_0F_01_07*/{ 0x116, 34495 }, + /*II_0F_01_C1*/{ 0x117, 1735 }, + /*II_0F_01_C2*/{ 0x117, 1743 }, + /*II_0F_01_C3*/{ 0x117, 1753 }, + /*II_0F_01_C4*/{ 0x117, 1763 }, + /*II_0F_01_C8*/{ 0x118, 1771 }, + /*II_0F_01_C9*/{ 0x118, 1780 }, + /*II_0F_01_D0*/{ 0x88, 1787 }, + /*II_0F_01_D1*/{ 0x88, 1795 }, + /*II_0F_01_D4*/{ 0x117, 1803 }, + /*II_0F_01_D5*/{ 0x119, 1811 }, + /*II_0F_01_D8*/{ 0x11a, 1817 }, + /*II_0F_01_D9*/{ 0x11b, 1824 }, + /*II_0F_01_DA*/{ 0x11c, 1833 }, + /*II_0F_01_DB*/{ 0x11c, 1841 }, + /*II_0F_01_DC*/{ 0x11b, 1849 }, + /*II_0F_01_DD*/{ 0x11b, 1855 }, + /*II_0F_01_DE*/{ 0x11c, 1861 }, + /*II_0F_01_DF*/{ 0x11d, 1869 }, + /*II_0F_01_F8*/{ 0x11e, 1878 }, + /*II_0F_01_F9*/{ 0x11e, 1886 }, + /*II_0F_0D_00*/{ 0x11f, 1894 }, + /*II_0F_0D_01*/{ 0x11f, 1904 }, + /*II_0F_0F_0C*/{ 0x120, 1915 }, + /*II_0F_0F_0D*/{ 0x121, 1922 }, + /*II_0F_0F_1C*/{ 0x120, 1929 }, + /*II_0F_0F_1D*/{ 0x121, 1936 }, + /*II_0F_0F_8A*/{ 0x120, 1943 }, + /*II_0F_0F_8E*/{ 0x120, 1951 }, + /*II_0F_0F_90*/{ 0x121, 1960 }, + /*II_0F_0F_94*/{ 0x121, 1969 }, + /*II_0F_0F_96*/{ 0x121, 1976 }, + /*II_0F_0F_97*/{ 0x121, 1983 }, + /*II_0F_0F_9A*/{ 0x121, 1992 }, + /*II_0F_0F_9E*/{ 0x121, 1999 }, + /*II_0F_0F_A0*/{ 0x121, 2006 }, + /*II_0F_0F_A4*/{ 0x121, 2015 }, + /*II_0F_0F_A6*/{ 0x121, 2022 }, + /*II_0F_0F_A7*/{ 0x121, 2032 }, + /*II_0F_0F_AA*/{ 0x121, 2042 }, + /*II_0F_0F_AE*/{ 0x121, 2050 }, + /*II_0F_0F_B0*/{ 0x121, 2057 }, + /*II_0F_0F_B4*/{ 0x121, 2066 }, + /*II_0F_0F_B6*/{ 0x121, 2073 }, + /*II_0F_0F_B7*/{ 0x121, 2083 }, + /*II_0F_0F_BB*/{ 0x120, 2092 }, + /*II_0F_0F_BF*/{ 0x121, 2100 }, + /*II_0F_10*/{ 0x122, 2109 }, + /*II_66_0F_10*/{ 0x123, 2117 }, + /*II_F3_0F_10*/{ 0x124, 2125 }, + /*II_F2_0F_10*/{ 0x125, 2132 }, + /*II_0F_11*/{ 0x12a, 2109 }, + /*II_66_0F_11*/{ 0x12b, 2117 }, + /*II_F3_0F_11*/{ 0x12c, 2125 }, + /*II_F2_0F_11*/{ 0x12d, 2132 }, + /*II_66_0F_12*/{ 0x132, 2190 }, + /*II_F3_0F_12*/{ 0x133, 2198 }, + /*II_F2_0F_12*/{ 0x133, 2208 }, + /*II_0F_13*/{ 0x137, 2182 }, + /*II_66_0F_13*/{ 0x138, 2190 }, + /*II_0F_14*/{ 0x13a, 2266 }, + /*II_66_0F_14*/{ 0x13b, 2276 }, + /*II_0F_15*/{ 0x13a, 2308 }, + /*II_66_0F_15*/{ 0x13b, 2318 }, + /*II_66_0F_16*/{ 0x132, 2367 }, + /*II_F3_0F_16*/{ 0x13d, 2375 }, + /*II_0F_17*/{ 0x137, 2359 }, + /*II_66_0F_17*/{ 0x138, 2367 }, + /*II_0F_18_00*/{ 0x13e, 2424 }, + /*II_0F_18_01*/{ 0x13e, 2437 }, + /*II_0F_18_02*/{ 0x13e, 2449 }, + /*II_0F_18_03*/{ 0x13e, 2461 }, + /*II_0F_28*/{ 0x122, 2473 }, + /*II_66_0F_28*/{ 0x123, 2481 }, + /*II_0F_29*/{ 0x12a, 2473 }, + /*II_66_0F_29*/{ 0x12b, 2481 }, + /*II_0F_2A*/{ 0x13f, 2507 }, + /*II_66_0F_2A*/{ 0x140, 2517 }, + /*II_F3_0F_2A*/{ 0x141, 2527 }, + /*II_F2_0F_2A*/{ 0x142, 2537 }, + /*II_0F_2B*/{ 0x143, 2569 }, + /*II_66_0F_2B*/{ 0x144, 2578 }, + /*II_F3_0F_2B*/{ 0x145, 2587 }, + /*II_F2_0F_2B*/{ 0x146, 2596 }, + /*II_0F_2C*/{ 0x148, 2625 }, + /*II_66_0F_2C*/{ 0x149, 2636 }, + /*II_F3_0F_2C*/{ 0x14a, 2647 }, + /*II_F2_0F_2C*/{ 0x14b, 2658 }, + /*II_0F_2D*/{ 0x148, 2693 }, + /*II_66_0F_2D*/{ 0x13b, 2703 }, + /*II_F3_0F_2D*/{ 0x14a, 2713 }, + /*II_F2_0F_2D*/{ 0x14b, 2723 }, + /*II_0F_2E*/{ 0x14d, 2755 }, + /*II_66_0F_2E*/{ 0x14e, 2764 }, + /*II_0F_2F*/{ 0x14d, 2793 }, + /*II_66_0F_2F*/{ 0x14e, 2801 }, + /*II_0F_50*/{ 0x151, 2827 }, + /*II_66_0F_50*/{ 0x152, 2837 }, + /*II_0F_51*/{ 0x13a, 2869 }, + /*II_66_0F_51*/{ 0x13b, 2877 }, + /*II_F3_0F_51*/{ 0x154, 2885 }, + /*II_F2_0F_51*/{ 0x14e, 2893 }, + /*II_0F_52*/{ 0x13a, 2937 }, + /*II_F3_0F_52*/{ 0x154, 2946 }, + /*II_0F_53*/{ 0x13a, 2975 }, + /*II_F3_0F_53*/{ 0x154, 2982 }, + /*II_0F_54*/{ 0x13a, 3005 }, + /*II_66_0F_54*/{ 0x13b, 3012 }, + /*II_0F_55*/{ 0x13a, 3035 }, + /*II_66_0F_55*/{ 0x13b, 3043 }, + /*II_0F_56*/{ 0x13a, 3069 }, + /*II_66_0F_56*/{ 0x13b, 3075 }, + /*II_0F_57*/{ 0x13a, 3095 }, + /*II_66_0F_57*/{ 0x13b, 3102 }, + /*II_0F_58*/{ 0x13a, 3125 }, + /*II_66_0F_58*/{ 0x13b, 3132 }, + /*II_F3_0F_58*/{ 0x154, 3139 }, + /*II_F2_0F_58*/{ 0x14e, 3146 }, + /*II_0F_59*/{ 0x13a, 3185 }, + /*II_66_0F_59*/{ 0x13b, 3192 }, + /*II_F3_0F_59*/{ 0x154, 3199 }, + /*II_F2_0F_59*/{ 0x14e, 3206 }, + /*II_0F_5A*/{ 0x14e, 3245 }, + /*II_66_0F_5A*/{ 0x13b, 3255 }, + /*II_F3_0F_5A*/{ 0x155, 3265 }, + /*II_F2_0F_5A*/{ 0x14e, 3275 }, + /*II_0F_5B*/{ 0x13b, 3329 }, + /*II_66_0F_5B*/{ 0x13b, 3339 }, + /*II_F3_0F_5B*/{ 0x13b, 3349 }, + /*II_0F_5C*/{ 0x13a, 3394 }, + /*II_66_0F_5C*/{ 0x13b, 3401 }, + /*II_F3_0F_5C*/{ 0x154, 3408 }, + /*II_F2_0F_5C*/{ 0x14e, 3415 }, + /*II_0F_5D*/{ 0x13a, 3454 }, + /*II_66_0F_5D*/{ 0x13b, 3461 }, + /*II_F3_0F_5D*/{ 0x154, 3468 }, + /*II_F2_0F_5D*/{ 0x14e, 3475 }, + /*II_0F_5E*/{ 0x13a, 3514 }, + /*II_66_0F_5E*/{ 0x13b, 3521 }, + /*II_F3_0F_5E*/{ 0x154, 3528 }, + /*II_F2_0F_5E*/{ 0x14e, 3535 }, + /*II_0F_5F*/{ 0x13a, 3574 }, + /*II_66_0F_5F*/{ 0x13b, 3581 }, + /*II_F3_0F_5F*/{ 0x154, 3588 }, + /*II_F2_0F_5F*/{ 0x14e, 3595 }, + /*II_0F_60*/{ 0x158, 3634 }, + /*II_66_0F_60*/{ 0x13b, 3634 }, + /*II_0F_61*/{ 0x158, 3657 }, + /*II_66_0F_61*/{ 0x13b, 3657 }, + /*II_0F_62*/{ 0x158, 3680 }, + /*II_66_0F_62*/{ 0x13b, 3680 }, + /*II_0F_63*/{ 0x159, 3703 }, + /*II_66_0F_63*/{ 0x13b, 3703 }, + /*II_0F_64*/{ 0x159, 3724 }, + /*II_66_0F_64*/{ 0x13b, 3724 }, + /*II_0F_65*/{ 0x159, 3743 }, + /*II_66_0F_65*/{ 0x13b, 3743 }, + /*II_0F_66*/{ 0x159, 3762 }, + /*II_66_0F_66*/{ 0x13b, 3762 }, + /*II_0F_67*/{ 0x159, 3781 }, + /*II_66_0F_67*/{ 0x13b, 3781 }, + /*II_0F_68*/{ 0x159, 3802 }, + /*II_66_0F_68*/{ 0x13b, 3802 }, + /*II_0F_69*/{ 0x159, 3825 }, + /*II_66_0F_69*/{ 0x13b, 3825 }, + /*II_0F_6A*/{ 0x159, 3848 }, + /*II_66_0F_6A*/{ 0x13b, 3848 }, + /*II_0F_6B*/{ 0x159, 3871 }, + /*II_66_0F_6B*/{ 0x13b, 3871 }, + /*II_66_0F_6C*/{ 0x13b, 3892 }, + /*II_66_0F_6D*/{ 0x13b, 3917 }, + /*II_0F_6F*/{ 0x15d, 3948 }, + /*II_66_0F_6F*/{ 0x123, 3968 }, + /*II_F3_0F_6F*/{ 0x123, 3976 }, + /*II_0F_74*/{ 0x159, 4065 }, + /*II_66_0F_74*/{ 0x13b, 4065 }, + /*II_0F_75*/{ 0x159, 4084 }, + /*II_66_0F_75*/{ 0x13b, 4084 }, + /*II_0F_76*/{ 0x159, 4103 }, + /*II_66_0F_76*/{ 0x13b, 4103 }, + /*II_0F_77*/{ 0x161, 4122 }, + /*II_0F_78*/{ 0x163, 4150 }, + /*II_0F_79*/{ 0x166, 4174 }, + /*II_66_0F_79*/{ 0x167, 4158 }, + /*II_F2_0F_79*/{ 0x168, 4165 }, + /*II_0F_7A_30*/{ 0x169, 4183 }, + /*II_0F_7A_31*/{ 0x16a, 4193 }, + /*II_66_0F_7C*/{ 0x16b, 4203 }, + /*II_F2_0F_7C*/{ 0x16b, 4211 }, + /*II_66_0F_7D*/{ 0x16b, 4237 }, + /*II_F2_0F_7D*/{ 0x16b, 4245 }, + /*II_F3_0F_7E*/{ 0x125, 3948 }, + /*II_0F_7F*/{ 0x16f, 3948 }, + /*II_66_0F_7F*/{ 0x12b, 3968 }, + /*II_F3_0F_7F*/{ 0x12b, 3976 }, + /*II_F3_0F_B8*/{ 0x173, 4360 }, + /*II_0F_BA_04*/{ 0x174, 872 }, + /*II_0F_BA_05*/{ 0x175, 887 }, + /*II_0F_BA_06*/{ 0x175, 912 }, + /*II_0F_BA_07*/{ 0x175, 934 }, + /*II_0F_BC*/{ 0x176, 4368 }, + /*II_F3_0F_BC*/{ 0x177, 4373 }, + /*II_0F_BD*/{ 0x176, 4380 }, + /*II_F3_0F_BD*/{ 0x178, 4385 }, + /*II_0F_C7_07*/{ 0x188, 6407 }, + /*II_66_0F_D0*/{ 0x16b, 6416 }, + /*II_F2_0F_D0*/{ 0x16b, 6426 }, + /*II_0F_D1*/{ 0x159, 6458 }, + /*II_66_0F_D1*/{ 0x13b, 6458 }, + /*II_0F_D2*/{ 0x159, 6473 }, + /*II_66_0F_D2*/{ 0x13b, 6473 }, + /*II_0F_D3*/{ 0x159, 6488 }, + /*II_66_0F_D3*/{ 0x13b, 6488 }, + /*II_0F_D4*/{ 0x14e, 6503 }, + /*II_66_0F_D4*/{ 0x13b, 6503 }, + /*II_0F_D5*/{ 0x159, 6518 }, + /*II_66_0F_D5*/{ 0x13b, 6518 }, + /*II_66_0F_D6*/{ 0x12d, 3948 }, + /*II_F3_0F_D6*/{ 0x189, 6535 }, + /*II_F2_0F_D6*/{ 0x18a, 6544 }, + /*II_0F_D7*/{ 0x18c, 6553 }, + /*II_66_0F_D7*/{ 0x18d, 6553 }, + /*II_0F_D8*/{ 0x159, 6574 }, + /*II_66_0F_D8*/{ 0x13b, 6574 }, + /*II_0F_D9*/{ 0x159, 6593 }, + /*II_66_0F_D9*/{ 0x13b, 6593 }, + /*II_0F_DA*/{ 0x18f, 6612 }, + /*II_66_0F_DA*/{ 0x13b, 6612 }, + /*II_0F_DB*/{ 0x159, 6629 }, + /*II_66_0F_DB*/{ 0x13b, 6629 }, + /*II_0F_DC*/{ 0x159, 6642 }, + /*II_66_0F_DC*/{ 0x13b, 6642 }, + /*II_0F_DD*/{ 0x159, 6661 }, + /*II_66_0F_DD*/{ 0x13b, 6661 }, + /*II_0F_DE*/{ 0x18f, 6670 }, + /*II_66_0F_DE*/{ 0x13b, 6670 }, + /*II_0F_DF*/{ 0x159, 6687 }, + /*II_66_0F_DF*/{ 0x13b, 6687 }, + /*II_0F_E0*/{ 0x18f, 6702 }, + /*II_66_0F_E0*/{ 0x13b, 6702 }, + /*II_0F_E1*/{ 0x159, 6717 }, + /*II_66_0F_E1*/{ 0x13b, 6717 }, + /*II_0F_E2*/{ 0x159, 6732 }, + /*II_66_0F_E2*/{ 0x13b, 6732 }, + /*II_0F_E3*/{ 0x18f, 6747 }, + /*II_66_0F_E3*/{ 0x13b, 6747 }, + /*II_0F_E4*/{ 0x18f, 6762 }, + /*II_66_0F_E4*/{ 0x13b, 6762 }, + /*II_0F_E5*/{ 0x159, 6781 }, + /*II_66_0F_E5*/{ 0x13b, 6781 }, + /*II_66_0F_E6*/{ 0x13b, 6798 }, + /*II_F3_0F_E6*/{ 0x14e, 6809 }, + /*II_F2_0F_E6*/{ 0x13b, 6819 }, + /*II_0F_E7*/{ 0x190, 6863 }, + /*II_66_0F_E7*/{ 0x144, 6871 }, + /*II_0F_E8*/{ 0x159, 6890 }, + /*II_66_0F_E8*/{ 0x13b, 6890 }, + /*II_0F_E9*/{ 0x159, 6907 }, + /*II_66_0F_E9*/{ 0x13b, 6907 }, + /*II_0F_EA*/{ 0x18f, 6924 }, + /*II_66_0F_EA*/{ 0x13b, 6924 }, + /*II_0F_EB*/{ 0x159, 6941 }, + /*II_66_0F_EB*/{ 0x13b, 6941 }, + /*II_0F_EC*/{ 0x159, 6952 }, + /*II_66_0F_EC*/{ 0x13b, 6952 }, + /*II_0F_ED*/{ 0x159, 6969 }, + /*II_66_0F_ED*/{ 0x13b, 6969 }, + /*II_0F_EE*/{ 0x18f, 6986 }, + /*II_66_0F_EE*/{ 0x13b, 6986 }, + /*II_0F_EF*/{ 0x159, 7003 }, + /*II_66_0F_EF*/{ 0x13b, 7003 }, + /*II_F2_0F_F0*/{ 0x191, 7016 }, + /*II_0F_F1*/{ 0x159, 7031 }, + /*II_66_0F_F1*/{ 0x13b, 7031 }, + /*II_0F_F2*/{ 0x159, 7046 }, + /*II_66_0F_F2*/{ 0x13b, 7046 }, + /*II_0F_F3*/{ 0x159, 7061 }, + /*II_66_0F_F3*/{ 0x13b, 7061 }, + /*II_0F_F4*/{ 0x193, 7076 }, + /*II_66_0F_F4*/{ 0x13b, 7076 }, + /*II_0F_F5*/{ 0x159, 7095 }, + /*II_66_0F_F5*/{ 0x13b, 7095 }, + /*II_0F_F6*/{ 0x18f, 7114 }, + /*II_66_0F_F6*/{ 0x13b, 7114 }, + /*II_0F_F7*/{ 0x194, 7131 }, + /*II_66_0F_F7*/{ 0x195, 7141 }, + /*II_0F_F8*/{ 0x159, 7166 }, + /*II_66_0F_F8*/{ 0x13b, 7166 }, + /*II_0F_F9*/{ 0x159, 7181 }, + /*II_66_0F_F9*/{ 0x13b, 7181 }, + /*II_0F_FA*/{ 0x159, 7196 }, + /*II_66_0F_FA*/{ 0x13b, 7196 }, + /*II_0F_FB*/{ 0x193, 7211 }, + /*II_66_0F_FB*/{ 0x13b, 7211 }, + /*II_0F_FC*/{ 0x159, 7226 }, + /*II_66_0F_FC*/{ 0x13b, 7226 }, + /*II_0F_FD*/{ 0x159, 7241 }, + /*II_66_0F_FD*/{ 0x13b, 7241 }, + /*II_0F_FE*/{ 0x159, 7256 }, + /*II_66_0F_FE*/{ 0x13b, 7256 }, + /*II_D9_06*/{ 0x197, 7271 }, + /*II_9B_D9_06*/{ 0x198, 7280 }, + /*II_D9_07*/{ 0xfd, 7288 }, + /*II_9B_D9_07*/{ 0x199, 7296 }, + /*II_DB_E2*/{ 0xeb, 7303 }, + /*II_9B_DB_E2*/{ 0x19a, 7311 }, + /*II_DB_E3*/{ 0xeb, 7318 }, + /*II_9B_DB_E3*/{ 0x19a, 7326 }, + /*II_DD_06*/{ 0x197, 7333 }, + /*II_9B_DD_06*/{ 0x198, 7341 }, + /*II_DD_07*/{ 0xfd, 7348 }, + /*II_9B_DD_07*/{ 0x199, 7356 }, + /*II_DF_E0*/{ 0x19b, 7348 }, + /*II_9B_DF_E0*/{ 0x19c, 7356 }, + /*II_0F_38_00*/{ 0x19d, 7363 }, + /*II_66_0F_38_00*/{ 0x19e, 7363 }, + /*II_0F_38_01*/{ 0x19d, 7380 }, + /*II_66_0F_38_01*/{ 0x19e, 7380 }, + /*II_0F_38_02*/{ 0x19d, 7397 }, + /*II_66_0F_38_02*/{ 0x19e, 7397 }, + /*II_0F_38_03*/{ 0x19d, 7414 }, + /*II_66_0F_38_03*/{ 0x19e, 7414 }, + /*II_0F_38_04*/{ 0x19d, 7433 }, + /*II_66_0F_38_04*/{ 0x19e, 7433 }, + /*II_0F_38_05*/{ 0x19d, 7456 }, + /*II_66_0F_38_05*/{ 0x19e, 7456 }, + /*II_0F_38_06*/{ 0x19d, 7473 }, + /*II_66_0F_38_06*/{ 0x19e, 7473 }, + /*II_0F_38_07*/{ 0x19d, 7490 }, + /*II_66_0F_38_07*/{ 0x19e, 7490 }, + /*II_0F_38_08*/{ 0x19d, 7509 }, + /*II_66_0F_38_08*/{ 0x19e, 7509 }, + /*II_0F_38_09*/{ 0x19d, 7526 }, + /*II_66_0F_38_09*/{ 0x19e, 7526 }, + /*II_0F_38_0A*/{ 0x19d, 7543 }, + /*II_66_0F_38_0A*/{ 0x19e, 7543 }, + /*II_0F_38_0B*/{ 0x19d, 7560 }, + /*II_66_0F_38_0B*/{ 0x19e, 7560 }, + /*II_66_0F_38_17*/{ 0x1a0, 7651 }, + /*II_0F_38_1C*/{ 0x19d, 7710 }, + /*II_66_0F_38_1C*/{ 0x19e, 7710 }, + /*II_0F_38_1D*/{ 0x19d, 7725 }, + /*II_66_0F_38_1D*/{ 0x19e, 7725 }, + /*II_0F_38_1E*/{ 0x19d, 7740 }, + /*II_66_0F_38_1E*/{ 0x19e, 7740 }, + /*II_66_0F_38_20*/{ 0x1a5, 7755 }, + /*II_66_0F_38_21*/{ 0x1a6, 7776 }, + /*II_66_0F_38_22*/{ 0x1a7, 7797 }, + /*II_66_0F_38_23*/{ 0x1a5, 7818 }, + /*II_66_0F_38_24*/{ 0x1a6, 7839 }, + /*II_66_0F_38_25*/{ 0x1a5, 7860 }, + /*II_66_0F_38_28*/{ 0x1a9, 7881 }, + /*II_66_0F_38_29*/{ 0x1a9, 7898 }, + /*II_66_0F_38_2A*/{ 0x1aa, 7917 }, + /*II_66_0F_38_2B*/{ 0x1a9, 7938 }, + /*II_66_0F_38_30*/{ 0x1a5, 7983 }, + /*II_66_0F_38_31*/{ 0x1a6, 8004 }, + /*II_66_0F_38_32*/{ 0x1a7, 8025 }, + /*II_66_0F_38_33*/{ 0x1a5, 8046 }, + /*II_66_0F_38_34*/{ 0x1a6, 8067 }, + /*II_66_0F_38_35*/{ 0x1a5, 8088 }, + /*II_66_0F_38_37*/{ 0x1a0, 8109 }, + /*II_66_0F_38_38*/{ 0x1a9, 8128 }, + /*II_66_0F_38_39*/{ 0x1a9, 8145 }, + /*II_66_0F_38_3A*/{ 0x1a9, 8162 }, + /*II_66_0F_38_3B*/{ 0x1a9, 8179 }, + /*II_66_0F_38_3C*/{ 0x1a9, 8196 }, + /*II_66_0F_38_3D*/{ 0x1a9, 8213 }, + /*II_66_0F_38_3E*/{ 0x1a9, 8230 }, + /*II_66_0F_38_3F*/{ 0x1a9, 8247 }, + /*II_66_0F_38_40*/{ 0x1a9, 8264 }, + /*II_66_0F_38_41*/{ 0x1a9, 8281 }, + /*II_66_0F_38_80*/{ 0x1ad, 8306 }, + /*II_66_0F_38_81*/{ 0x1ad, 8314 }, + /*II_66_0F_38_82*/{ 0x1ad, 8323 }, + /*II_66_0F_38_DB*/{ 0x1b0, 9172 }, + /*II_66_0F_38_DC*/{ 0x1b0, 9189 }, + /*II_66_0F_38_DD*/{ 0x1b0, 9206 }, + /*II_66_0F_38_DE*/{ 0x1b0, 9231 }, + /*II_66_0F_38_DF*/{ 0x1b0, 9248 }, + /*II_0F_38_F0*/{ 0x1b3, 9273 }, + /*II_F2_0F_38_F0*/{ 0x1b4, 9280 }, + /*II_0F_38_F1*/{ 0x1b5, 9273 }, + /*II_F2_0F_38_F1*/{ 0x1b6, 9280 }, + /*II_0F_71_02*/{ 0x1cd, 6458 }, + /*II_66_0F_71_02*/{ 0x1ce, 6458 }, + /*II_0F_71_04*/{ 0x1cd, 6717 }, + /*II_66_0F_71_04*/{ 0x1ce, 6717 }, + /*II_0F_71_06*/{ 0x1cd, 7031 }, + /*II_66_0F_71_06*/{ 0x1ce, 7031 }, + /*II_0F_72_02*/{ 0x1cd, 6473 }, + /*II_66_0F_72_02*/{ 0x1ce, 6473 }, + /*II_0F_72_04*/{ 0x1cd, 6732 }, + /*II_66_0F_72_04*/{ 0x1ce, 6732 }, + /*II_0F_72_06*/{ 0x1cd, 7046 }, + /*II_66_0F_72_06*/{ 0x1ce, 7046 }, + /*II_0F_73_02*/{ 0x1cd, 6488 }, + /*II_66_0F_73_02*/{ 0x1ce, 6488 }, + /*II_66_0F_73_03*/{ 0x1ce, 9852 }, + /*II_0F_73_06*/{ 0x1cd, 7061 }, + /*II_66_0F_73_06*/{ 0x1ce, 7061 }, + /*II_66_0F_73_07*/{ 0x1ce, 9869 }, + /*II_F3_0F_AE_00*/{ 0x1d0, 9904 }, + /*II_F3_0F_AE_01*/{ 0x1d0, 9934 }, + /*II_0F_AE_02*/{ 0x116, 9944 }, + /*II_F3_0F_AE_02*/{ 0x1d0, 9953 }, + /*II_0F_AE_03*/{ 0x116, 9973 }, + /*II_F3_0F_AE_03*/{ 0x1d0, 9982 }, + /*II_0F_C7_06*/{ 0x1d2, 10002 }, + /*II_66_0F_C7_06*/{ 0x188, 10011 }, + /*II_F3_0F_C7_06*/{ 0x188, 10020 } +}; + +_InstInfoEx InstInfosEx[381] = { + /*II_69*/{ { 0x34, 117 }, 0x0, 3, 0, 0, 0 }, + /*II_6B*/{ { 0x34, 117 }, 0x0, 5, 0, 0, 0 }, + /*II_98*/{ { 0x4e, 228 }, 0x0, 0, 0, 233, 239 }, + /*II_99*/{ { 0x4e, 245 }, 0x0, 0, 0, 250, 255 }, + /*II_E3*/{ { 0x76, 427 }, 0x0, 0, 0, 433, 440 }, + /*II_0F_A4*/{ { 0xac, 876 }, 0x0, 1, 0, 0, 0 }, + /*II_0F_A5*/{ { 0xac, 876 }, 0x0, 52, 0, 0, 0 }, + /*II_0F_AC*/{ { 0xac, 892 }, 0x0, 1, 0, 0, 0 }, + /*II_0F_AD*/{ { 0xac, 892 }, 0x0, 52, 0, 0, 0 }, + /*II_V_0F_10*/{ { 0x126, 2139 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_10*/{ { 0x126, 2148 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_10*/{ { 0x127, 2157 }, 0x20, 69, 0, 0, 0 }, + /*II_V_F2_0F_10*/{ { 0x127, 2165 }, 0x20, 69, 0, 0, 0 }, + /*II_VRR_F3_0F_10*/{ { 0x128, 2157 }, 0x60, 0, 0, 0, 0 }, + /*II_VRR_F2_0F_10*/{ { 0x129, 2165 }, 0x60, 0, 0, 0, 0 }, + /*II_V_0F_11*/{ { 0x12e, 2139 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_11*/{ { 0x12e, 2148 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_11*/{ { 0x127, 2157 }, 0x20, 69, 0, 0, 0 }, + /*II_V_F2_0F_11*/{ { 0x127, 2165 }, 0x20, 69, 0, 0, 0 }, + /*II_VRR_F3_0F_11*/{ { 0x12f, 2157 }, 0x60, 0, 0, 0, 0 }, + /*II_VRR_F2_0F_11*/{ { 0x130, 2165 }, 0x60, 0, 0, 0, 0 }, + /*II_0F_12*/{ { 0x131, 2173 }, 0x0, 0, 0, 2182, 0 }, + /*II_V_0F_12*/{ { 0x134, 2217 }, 0x0, 72, 0, 2227, 0 }, + /*II_V_66_0F_12*/{ { 0x135, 2236 }, 0x0, 46, 0, 0, 0 }, + /*II_V_F3_0F_12*/{ { 0x126, 2245 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F2_0F_12*/{ { 0x136, 2256 }, 0x41, 0, 0, 0, 0 }, + /*II_V_0F_13*/{ { 0x139, 2227 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_13*/{ { 0x139, 2236 }, 0x40, 0, 0, 0, 0 }, + /*II_V_0F_14*/{ { 0x13c, 2286 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_14*/{ { 0x13c, 2297 }, 0x1, 90, 0, 0, 0 }, + /*II_V_0F_15*/{ { 0x13c, 2328 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_15*/{ { 0x13c, 2339 }, 0x1, 90, 0, 0, 0 }, + /*II_0F_16*/{ { 0x131, 2350 }, 0x0, 0, 0, 2359, 0 }, + /*II_V_0F_16*/{ { 0x134, 2385 }, 0x0, 72, 0, 2395, 0 }, + /*II_V_66_0F_16*/{ { 0x135, 2404 }, 0x0, 46, 0, 0, 0 }, + /*II_V_F3_0F_16*/{ { 0x126, 2413 }, 0x41, 0, 0, 0, 0 }, + /*II_V_0F_17*/{ { 0x139, 2395 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_17*/{ { 0x139, 2404 }, 0x40, 0, 0, 0, 0 }, + /*II_V_0F_28*/{ { 0x126, 2489 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_28*/{ { 0x126, 2498 }, 0x41, 0, 0, 0, 0 }, + /*II_V_0F_29*/{ { 0x12e, 2489 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_29*/{ { 0x12e, 2498 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_2A*/{ { 0x135, 2547 }, 0x2, 79, 0, 0, 0 }, + /*II_V_F2_0F_2A*/{ { 0x135, 2558 }, 0x2, 79, 0, 0, 0 }, + /*II_V_0F_2B*/{ { 0x147, 2605 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_2B*/{ { 0x147, 2615 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_2C*/{ { 0x14c, 2669 }, 0x42, 0, 0, 0, 0 }, + /*II_V_F2_0F_2C*/{ { 0x14c, 2681 }, 0x42, 0, 0, 0, 0 }, + /*II_V_F3_0F_2D*/{ { 0x14c, 2733 }, 0x42, 0, 0, 0, 0 }, + /*II_V_F2_0F_2D*/{ { 0x14c, 2744 }, 0x42, 0, 0, 0, 0 }, + /*II_V_0F_2E*/{ { 0x14f, 2773 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_2E*/{ { 0x150, 2783 }, 0x40, 0, 0, 0, 0 }, + /*II_V_0F_2F*/{ { 0x14f, 2809 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_2F*/{ { 0x150, 2818 }, 0x40, 0, 0, 0, 0 }, + /*II_V_0F_50*/{ { 0x153, 2847 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_50*/{ { 0x153, 2858 }, 0x41, 0, 0, 0, 0 }, + /*II_V_0F_51*/{ { 0x126, 2901 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_51*/{ { 0x126, 2910 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_51*/{ { 0x135, 2919 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_51*/{ { 0x135, 2928 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_52*/{ { 0x126, 2955 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_52*/{ { 0x135, 2965 }, 0x0, 71, 0, 0, 0 }, + /*II_V_0F_53*/{ { 0x126, 2989 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_53*/{ { 0x135, 2997 }, 0x0, 71, 0, 0, 0 }, + /*II_V_0F_54*/{ { 0x13c, 3019 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_54*/{ { 0x13c, 3027 }, 0x1, 90, 0, 0, 0 }, + /*II_V_0F_55*/{ { 0x13c, 3051 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_55*/{ { 0x13c, 3060 }, 0x1, 90, 0, 0, 0 }, + /*II_V_0F_56*/{ { 0x13c, 3081 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_56*/{ { 0x13c, 3088 }, 0x1, 90, 0, 0, 0 }, + /*II_V_0F_57*/{ { 0x13c, 3109 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_57*/{ { 0x13c, 3117 }, 0x1, 90, 0, 0, 0 }, + /*II_V_0F_58*/{ { 0x13c, 3153 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_58*/{ { 0x13c, 3161 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_58*/{ { 0x135, 3169 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_58*/{ { 0x135, 3177 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_59*/{ { 0x13c, 3213 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_59*/{ { 0x13c, 3221 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_59*/{ { 0x135, 3229 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_59*/{ { 0x135, 3237 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_5A*/{ { 0x156, 3285 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_5A*/{ { 0x157, 3296 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_5A*/{ { 0x135, 3307 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_5A*/{ { 0x135, 3318 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_5B*/{ { 0x126, 3360 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_5B*/{ { 0x126, 3371 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_5B*/{ { 0x126, 3382 }, 0x41, 0, 0, 0, 0 }, + /*II_V_0F_5C*/{ { 0x13c, 3422 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_5C*/{ { 0x13c, 3430 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_5C*/{ { 0x135, 3438 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_5C*/{ { 0x135, 3446 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_5D*/{ { 0x13c, 3482 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_5D*/{ { 0x13c, 3490 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_5D*/{ { 0x135, 3498 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_5D*/{ { 0x135, 3506 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_5E*/{ { 0x13c, 3542 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_5E*/{ { 0x13c, 3550 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_5E*/{ { 0x135, 3558 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_5E*/{ { 0x135, 3566 }, 0x0, 72, 0, 0, 0 }, + /*II_V_0F_5F*/{ { 0x13c, 3602 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_5F*/{ { 0x13c, 3610 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F3_0F_5F*/{ { 0x135, 3618 }, 0x0, 71, 0, 0, 0 }, + /*II_V_F2_0F_5F*/{ { 0x135, 3626 }, 0x0, 72, 0, 0, 0 }, + /*II_V_66_0F_60*/{ { 0x135, 3645 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_61*/{ { 0x135, 3668 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_62*/{ { 0x135, 3691 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_63*/{ { 0x135, 3713 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_64*/{ { 0x135, 3733 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_65*/{ { 0x135, 3752 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_66*/{ { 0x135, 3771 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_67*/{ { 0x135, 3791 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_68*/{ { 0x135, 3813 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_69*/{ { 0x135, 3836 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_6A*/{ { 0x135, 3859 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_6B*/{ { 0x135, 3881 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_6C*/{ { 0x135, 3904 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_6D*/{ { 0x135, 3929 }, 0x0, 73, 0, 0, 0 }, + /*II_0F_6E*/{ { 0x15a, 3942 }, 0x0, 0, 0, 0, 3948 }, + /*II_66_0F_6E*/{ { 0x15b, 3942 }, 0x0, 0, 0, 0, 3948 }, + /*II_V_66_0F_6E*/{ { 0x15c, 3954 }, 0x46, 0, 0, 3961, 0 }, + /*II_V_66_0F_6F*/{ { 0x126, 3984 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_6F*/{ { 0x126, 3993 }, 0x41, 0, 0, 0, 0 }, + /*II_0F_70*/{ { 0x15e, 4002 }, 0x0, 1, 0, 0, 0 }, + /*II_66_0F_70*/{ { 0x15f, 4010 }, 0x0, 1, 0, 0, 0 }, + /*II_F3_0F_70*/{ { 0x15f, 4018 }, 0x0, 1, 0, 0, 0 }, + /*II_F2_0F_70*/{ { 0x15f, 4027 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_70*/{ { 0x160, 4036 }, 0x40, 1, 0, 0, 0 }, + /*II_V_F3_0F_70*/{ { 0x160, 4045 }, 0x40, 1, 0, 0, 0 }, + /*II_V_F2_0F_70*/{ { 0x160, 4055 }, 0x40, 1, 0, 0, 0 }, + /*II_V_66_0F_74*/{ { 0x135, 4074 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_75*/{ { 0x135, 4093 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_76*/{ { 0x135, 4112 }, 0x0, 73, 0, 0, 0 }, + /*II_V_0F_77*/{ { 0x162, 4128 }, 0x49, 0, 0, 4140, 0 }, + /*II_66_0F_78*/{ { 0x164, 4158 }, 0x0, 8, 0, 0, 0 }, + /*II_F2_0F_78*/{ { 0x165, 4165 }, 0x0, 7, 8, 0, 0 }, + /*II_V_66_0F_7C*/{ { 0x13c, 4219 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F2_0F_7C*/{ { 0x13c, 4228 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_7D*/{ { 0x13c, 4253 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F2_0F_7D*/{ { 0x13c, 4262 }, 0x1, 90, 0, 0, 0 }, + /*II_0F_7E*/{ { 0x16c, 3942 }, 0x0, 0, 0, 0, 3948 }, + /*II_66_0F_7E*/{ { 0x16d, 3942 }, 0x0, 0, 0, 0, 3948 }, + /*II_V_66_0F_7E*/{ { 0x16e, 3954 }, 0x46, 0, 0, 3961, 0 }, + /*II_V_F3_0F_7E*/{ { 0x150, 3961 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_7F*/{ { 0x12e, 3984 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_7F*/{ { 0x12e, 3993 }, 0x41, 0, 0, 0, 0 }, + /*II_0F_AE_04*/{ { 0x170, 4271 }, 0x0, 0, 0, 0, 4278 }, + /*II_0F_AE_05*/{ { 0x171, 4287 }, 0x0, 0, 0, 4295, 4303 }, + /*II_0F_AE_06*/{ { 0x171, 4313 }, 0x0, 0, 0, 4321, 4331 }, + /*II_0F_AE_07*/{ { 0x172, 4343 }, 0x0, 0, 0, 4351, 0 }, + /*II_0F_C2*/{ { 0x179, 4392 }, 0x0, 0, 0, 4401, 4410 }, + /*II_66_0F_C2*/{ { 0x17a, 4471 }, 0x0, 0, 0, 4480, 4489 }, + /*II_F3_0F_C2*/{ { 0x17b, 4550 }, 0x0, 0, 0, 4559, 4568 }, + /*II_F2_0F_C2*/{ { 0x17c, 4629 }, 0x0, 0, 0, 4638, 4647 }, + /*II_V_0F_C2*/{ { 0x17d, 4708 }, 0x1, 90, 0, 4718, 4728 }, + /*II_V_66_0F_C2*/{ { 0x17d, 5110 }, 0x1, 90, 0, 5120, 5130 }, + /*II_V_F3_0F_C2*/{ { 0x17e, 5512 }, 0x0, 71, 0, 5522, 5532 }, + /*II_V_F2_0F_C2*/{ { 0x17e, 5914 }, 0x0, 72, 0, 5924, 5934 }, + /*II_0F_C4*/{ { 0x17f, 6316 }, 0x0, 1, 0, 0, 0 }, + /*II_66_0F_C4*/{ { 0x180, 6316 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_C4*/{ { 0x181, 6324 }, 0x0, 25, 1, 0, 0 }, + /*II_0F_C5*/{ { 0x182, 6333 }, 0x0, 1, 0, 0, 0 }, + /*II_66_0F_C5*/{ { 0x183, 6333 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_C5*/{ { 0x184, 6341 }, 0x40, 1, 0, 0, 0 }, + /*II_0F_C6*/{ { 0x185, 6350 }, 0x0, 1, 0, 0, 0 }, + /*II_66_0F_C6*/{ { 0x15f, 6358 }, 0x0, 1, 0, 0, 0 }, + /*II_V_0F_C6*/{ { 0x186, 6366 }, 0x1, 90, 1, 0, 0 }, + /*II_V_66_0F_C6*/{ { 0x186, 6375 }, 0x1, 90, 1, 0, 0 }, + /*II_0F_C7_01*/{ { 0x187, 6384 }, 0x0, 0, 0, 0, 6395 }, + /*II_V_66_0F_D0*/{ { 0x13c, 6436 }, 0x1, 90, 0, 0, 0 }, + /*II_V_F2_0F_D0*/{ { 0x13c, 6447 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_D1*/{ { 0x135, 6465 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D2*/{ { 0x135, 6480 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D3*/{ { 0x135, 6495 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D4*/{ { 0x135, 6510 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D5*/{ { 0x135, 6526 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D6*/{ { 0x18b, 3961 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_D7*/{ { 0x18e, 6563 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_D8*/{ { 0x135, 6583 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_D9*/{ { 0x135, 6602 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DA*/{ { 0x135, 6620 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DB*/{ { 0x135, 6635 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DC*/{ { 0x135, 6651 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DD*/{ { 0x135, 6651 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DE*/{ { 0x135, 6678 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_DF*/{ { 0x135, 6694 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E0*/{ { 0x135, 6709 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E1*/{ { 0x135, 6724 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E2*/{ { 0x135, 6739 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E3*/{ { 0x135, 6754 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E4*/{ { 0x135, 6771 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E5*/{ { 0x135, 6789 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E6*/{ { 0x157, 6829 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F3_0F_E6*/{ { 0x156, 6841 }, 0x41, 0, 0, 0, 0 }, + /*II_V_F2_0F_E6*/{ { 0x157, 6852 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_E7*/{ { 0x147, 6880 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_E8*/{ { 0x135, 6898 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_E9*/{ { 0x135, 6915 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_EA*/{ { 0x135, 6932 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_EB*/{ { 0x135, 6946 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_EC*/{ { 0x135, 6960 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_ED*/{ { 0x135, 6977 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_EE*/{ { 0x135, 6994 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_EF*/{ { 0x135, 7009 }, 0x0, 73, 0, 0, 0 }, + /*II_V_F2_0F_F0*/{ { 0x192, 7023 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_F1*/{ { 0x135, 7038 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F2*/{ { 0x135, 7053 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F3*/{ { 0x135, 7068 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F4*/{ { 0x135, 7085 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F5*/{ { 0x135, 7104 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F6*/{ { 0x135, 7122 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F7*/{ { 0x196, 7153 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_F8*/{ { 0x135, 7173 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_F9*/{ { 0x135, 7188 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_FA*/{ { 0x135, 7203 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_FB*/{ { 0x135, 7218 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_FC*/{ { 0x135, 7233 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_FD*/{ { 0x135, 7248 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_FE*/{ { 0x135, 7263 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_00*/{ { 0x135, 7371 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_01*/{ { 0x135, 7388 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_02*/{ { 0x135, 7405 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_03*/{ { 0x135, 7423 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_04*/{ { 0x135, 7444 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_05*/{ { 0x135, 7464 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_06*/{ { 0x135, 7481 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_07*/{ { 0x135, 7499 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_08*/{ { 0x135, 7517 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_09*/{ { 0x135, 7534 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_0A*/{ { 0x135, 7551 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_0B*/{ { 0x135, 7570 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_0C*/{ { 0x13c, 7581 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_38_0D*/{ { 0x13c, 7592 }, 0x1, 90, 0, 0, 0 }, + /*II_V_66_0F_38_0E*/{ { 0x126, 7603 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_38_0F*/{ { 0x126, 7612 }, 0x41, 0, 0, 0, 0 }, + /*II_66_0F_38_10*/{ { 0x19f, 7621 }, 0x0, 74, 0, 0, 0 }, + /*II_66_0F_38_14*/{ { 0x19f, 7631 }, 0x0, 74, 0, 0, 0 }, + /*II_66_0F_38_15*/{ { 0x19f, 7641 }, 0x0, 74, 0, 0, 0 }, + /*II_V_66_0F_38_17*/{ { 0x126, 7658 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_38_18*/{ { 0x1a1, 7666 }, 0x41, 0, 0, 0, 0 }, + /*II_V_66_0F_38_19*/{ { 0x1a2, 7680 }, 0x50, 0, 0, 0, 0 }, + /*II_V_66_0F_38_1A*/{ { 0x1a3, 7694 }, 0x50, 0, 0, 0, 0 }, + /*II_V_66_0F_38_1C*/{ { 0x1a4, 7717 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_1D*/{ { 0x1a4, 7732 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_1E*/{ { 0x1a4, 7747 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_20*/{ { 0x150, 7765 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_21*/{ { 0x14f, 7786 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_22*/{ { 0x1a8, 7807 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_23*/{ { 0x150, 7828 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_24*/{ { 0x14f, 7849 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_25*/{ { 0x150, 7870 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_28*/{ { 0x135, 7889 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_29*/{ { 0x135, 7907 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_2A*/{ { 0x1ab, 7927 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_2B*/{ { 0x135, 7948 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_2C*/{ { 0x13c, 7959 }, 0x1, 92, 0, 0, 0 }, + /*II_V_66_0F_38_2D*/{ { 0x13c, 7971 }, 0x1, 92, 0, 0, 0 }, + /*II_V_66_0F_38_2E*/{ { 0x1ac, 7959 }, 0x1, 83, 0, 0, 0 }, + /*II_V_66_0F_38_2F*/{ { 0x1ac, 7971 }, 0x1, 83, 0, 0, 0 }, + /*II_V_66_0F_38_30*/{ { 0x150, 7993 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_31*/{ { 0x14f, 8014 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_32*/{ { 0x1a8, 8035 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_33*/{ { 0x150, 8056 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_34*/{ { 0x14f, 8077 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_35*/{ { 0x150, 8098 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_37*/{ { 0x135, 8118 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_38*/{ { 0x135, 8136 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_39*/{ { 0x135, 8153 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3A*/{ { 0x135, 8170 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3B*/{ { 0x135, 8187 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3C*/{ { 0x135, 8204 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3D*/{ { 0x135, 8221 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3E*/{ { 0x135, 8238 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_3F*/{ { 0x135, 8255 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_40*/{ { 0x135, 8272 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_41*/{ { 0x1a4, 8293 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_96*/{ { 0x1ae, 8332 }, 0x7, 90, 0, 8348, 0 }, + /*II_V_66_0F_38_97*/{ { 0x1ae, 8364 }, 0x7, 90, 0, 8380, 0 }, + /*II_V_66_0F_38_98*/{ { 0x1ae, 8396 }, 0x7, 90, 0, 8409, 0 }, + /*II_V_66_0F_38_99*/{ { 0x1af, 8422 }, 0x6, 80, 0, 8435, 0 }, + /*II_V_66_0F_38_9A*/{ { 0x1ae, 8448 }, 0x7, 90, 0, 8461, 0 }, + /*II_V_66_0F_38_9B*/{ { 0x1af, 8474 }, 0x6, 80, 0, 8487, 0 }, + /*II_V_66_0F_38_9C*/{ { 0x1ae, 8500 }, 0x7, 90, 0, 8514, 0 }, + /*II_V_66_0F_38_9D*/{ { 0x1af, 8528 }, 0x6, 80, 0, 8542, 0 }, + /*II_V_66_0F_38_9E*/{ { 0x1ae, 8556 }, 0x7, 90, 0, 8570, 0 }, + /*II_V_66_0F_38_9F*/{ { 0x1af, 8584 }, 0x6, 80, 0, 8598, 0 }, + /*II_V_66_0F_38_A6*/{ { 0x1ae, 8612 }, 0x7, 90, 0, 8628, 0 }, + /*II_V_66_0F_38_A7*/{ { 0x1ae, 8644 }, 0x7, 90, 0, 8660, 0 }, + /*II_V_66_0F_38_A8*/{ { 0x1ae, 8676 }, 0x7, 90, 0, 8689, 0 }, + /*II_V_66_0F_38_A9*/{ { 0x1af, 8702 }, 0x6, 80, 0, 8715, 0 }, + /*II_V_66_0F_38_AA*/{ { 0x1ae, 8728 }, 0x7, 90, 0, 8741, 0 }, + /*II_V_66_0F_38_AB*/{ { 0x1af, 8754 }, 0x6, 80, 0, 8767, 0 }, + /*II_V_66_0F_38_AC*/{ { 0x1ae, 8780 }, 0x7, 90, 0, 8794, 0 }, + /*II_V_66_0F_38_AD*/{ { 0x1af, 8808 }, 0x6, 80, 0, 8822, 0 }, + /*II_V_66_0F_38_AE*/{ { 0x1ae, 8836 }, 0x7, 90, 0, 8850, 0 }, + /*II_V_66_0F_38_AF*/{ { 0x1af, 8864 }, 0x6, 80, 0, 8878, 0 }, + /*II_V_66_0F_38_B6*/{ { 0x1ae, 8892 }, 0x7, 90, 0, 8908, 0 }, + /*II_V_66_0F_38_B7*/{ { 0x1ae, 8924 }, 0x7, 90, 0, 8940, 0 }, + /*II_V_66_0F_38_B8*/{ { 0x1ae, 8956 }, 0x7, 90, 0, 8969, 0 }, + /*II_V_66_0F_38_B9*/{ { 0x1af, 8982 }, 0x6, 80, 0, 8995, 0 }, + /*II_V_66_0F_38_BA*/{ { 0x1ae, 9008 }, 0x7, 90, 0, 9021, 0 }, + /*II_V_66_0F_38_BB*/{ { 0x1af, 9034 }, 0x6, 80, 0, 9047, 0 }, + /*II_V_66_0F_38_BC*/{ { 0x1ae, 9060 }, 0x7, 90, 0, 9074, 0 }, + /*II_V_66_0F_38_BD*/{ { 0x1af, 9088 }, 0x6, 80, 0, 9102, 0 }, + /*II_V_66_0F_38_BE*/{ { 0x1ae, 9116 }, 0x7, 90, 0, 9130, 0 }, + /*II_V_66_0F_38_BF*/{ { 0x1af, 9144 }, 0x6, 80, 0, 9158, 0 }, + /*II_V_66_0F_38_DB*/{ { 0x1b1, 9180 }, 0x40, 0, 0, 0, 0 }, + /*II_V_66_0F_38_DC*/{ { 0x1b2, 9197 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_DD*/{ { 0x1b2, 9218 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_DE*/{ { 0x1b2, 9239 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_38_DF*/{ { 0x1b2, 9260 }, 0x0, 73, 0, 0, 0 }, + /*II_V_66_0F_3A_04*/{ { 0x1b7, 7581 }, 0x41, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_05*/{ { 0x1b7, 7592 }, 0x41, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_06*/{ { 0x1b8, 9287 }, 0x10, 86, 1, 0, 0 }, + /*II_66_0F_3A_08*/{ { 0x19f, 9299 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_08*/{ { 0x1b7, 9308 }, 0x41, 1, 0, 0, 0 }, + /*II_66_0F_3A_09*/{ { 0x19f, 9318 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_09*/{ { 0x1b7, 9327 }, 0x41, 1, 0, 0, 0 }, + /*II_66_0F_3A_0A*/{ { 0x1b9, 9337 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0A*/{ { 0x181, 9346 }, 0x0, 71, 1, 0, 0 }, + /*II_66_0F_3A_0B*/{ { 0x1ba, 9356 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0B*/{ { 0x181, 9365 }, 0x0, 72, 1, 0, 0 }, + /*II_66_0F_3A_0C*/{ { 0x19f, 9375 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0C*/{ { 0x186, 9384 }, 0x1, 90, 1, 0, 0 }, + /*II_66_0F_3A_0D*/{ { 0x19f, 9394 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0D*/{ { 0x186, 9403 }, 0x1, 90, 1, 0, 0 }, + /*II_66_0F_3A_0E*/{ { 0x19f, 9413 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0E*/{ { 0x181, 9422 }, 0x0, 73, 1, 0, 0 }, + /*II_0F_3A_0F*/{ { 0x1bb, 9432 }, 0x0, 1, 0, 0, 0 }, + /*II_66_0F_3A_0F*/{ { 0x1bc, 9432 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_0F*/{ { 0x181, 9441 }, 0x0, 73, 1, 0, 0 }, + /*II_66_0F_3A_14*/{ { 0x1bd, 9451 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_14*/{ { 0x1be, 9459 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_15*/{ { 0x1bf, 6333 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_15*/{ { 0x1c0, 6341 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_16*/{ { 0x1c1, 9468 }, 0x0, 1, 0, 0, 9476 }, + /*II_V_66_0F_3A_16*/{ { 0x1c2, 9484 }, 0x46, 1, 0, 9493, 0 }, + /*II_66_0F_3A_17*/{ { 0x1c3, 9502 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_17*/{ { 0x1c4, 9513 }, 0x40, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_18*/{ { 0x1b8, 9525 }, 0x10, 73, 1, 0, 0 }, + /*II_V_66_0F_3A_19*/{ { 0x1c5, 9538 }, 0x50, 1, 0, 0, 0 }, + /*II_66_0F_3A_20*/{ { 0x1c6, 9552 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_20*/{ { 0x181, 9560 }, 0x0, 76, 1, 0, 0 }, + /*II_66_0F_3A_21*/{ { 0x1b9, 9569 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_21*/{ { 0x181, 9579 }, 0x0, 71, 1, 0, 0 }, + /*II_66_0F_3A_22*/{ { 0x1c7, 9590 }, 0x0, 1, 0, 0, 9598 }, + /*II_V_66_0F_3A_22*/{ { 0x181, 9606 }, 0x6, 79, 1, 9615, 0 }, + /*II_66_0F_3A_40*/{ { 0x19f, 9624 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_40*/{ { 0x186, 9630 }, 0x1, 90, 1, 0, 0 }, + /*II_66_0F_3A_41*/{ { 0x19f, 9637 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_41*/{ { 0x181, 9643 }, 0x0, 73, 1, 0, 0 }, + /*II_66_0F_3A_42*/{ { 0x19f, 9650 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_42*/{ { 0x181, 9659 }, 0x0, 73, 1, 0, 0 }, + /*II_66_0F_3A_44*/{ { 0x1c8, 9669 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_44*/{ { 0x1c9, 9680 }, 0x0, 73, 1, 0, 0 }, + /*II_V_66_0F_3A_4A*/{ { 0x186, 9692 }, 0x1, 90, 84, 0, 0 }, + /*II_V_66_0F_3A_4B*/{ { 0x186, 9703 }, 0x1, 90, 84, 0, 0 }, + /*II_V_66_0F_3A_4C*/{ { 0x181, 9714 }, 0x0, 73, 82, 0, 0 }, + /*II_66_0F_3A_60*/{ { 0x1ca, 9725 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_60*/{ { 0x160, 9736 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_61*/{ { 0x1ca, 9748 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_61*/{ { 0x160, 9759 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_62*/{ { 0x1ca, 9771 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_62*/{ { 0x160, 9782 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_63*/{ { 0x1ca, 9794 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_63*/{ { 0x160, 9805 }, 0x40, 1, 0, 0, 0 }, + /*II_66_0F_3A_DF*/{ { 0x1cb, 9817 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_3A_DF*/{ { 0x1cc, 9834 }, 0x40, 1, 0, 0, 0 }, + /*II_V_66_0F_71_02*/{ { 0x1cf, 6465 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_71_04*/{ { 0x1cf, 6724 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_71_06*/{ { 0x1cf, 7038 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_72_02*/{ { 0x1cf, 6480 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_72_04*/{ { 0x1cf, 6739 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_72_06*/{ { 0x1cf, 7053 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_73_02*/{ { 0x1cf, 6495 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_73_03*/{ { 0x1cf, 9860 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_73_06*/{ { 0x1cf, 7068 }, 0x0, 1, 0, 0, 0 }, + /*II_V_66_0F_73_07*/{ { 0x1cf, 9877 }, 0x0, 1, 0, 0, 0 }, + /*II_0F_AE_00*/{ { 0x170, 9886 }, 0x0, 0, 0, 0, 9894 }, + /*II_0F_AE_01*/{ { 0x170, 9914 }, 0x0, 0, 0, 0, 9923 }, + /*II_V_0F_AE_02*/{ { 0x1d1, 9963 }, 0x40, 0, 0, 0, 0 }, + /*II_V_0F_AE_03*/{ { 0x1d1, 9992 }, 0x40, 0, 0, 0, 0 } +}; + +_InstNode InstructionsTree[5688] = { + /* 0 - _00 */ 0x2000, + /* 1 - _01 */ 0x2001, + /* 2 - _02 */ 0x2002, + /* 3 - _03 */ 0x2003, + /* 4 - _04 */ 0x2004, + /* 5 - _05 */ 0x2005, + /* 6 - _06 */ 0x2006, + /* 7 - _07 */ 0x2007, + /* 8 - _08 */ 0x2008, + /* 9 - _09 */ 0x2009, + /* a - _0A */ 0x200a, + /* b - _0B */ 0x200b, + /* c - _0C */ 0x200c, + /* d - _0D */ 0x200d, + /* e - _0E */ 0x200e, + /* f - _0F */ 0x8100, + /* 10 - _10 */ 0x200f, + /* 11 - _11 */ 0x2010, + /* 12 - _12 */ 0x2011, + /* 13 - _13 */ 0x2012, + /* 14 - _14 */ 0x2013, + /* 15 - _15 */ 0x2014, + /* 16 - _16 */ 0x2015, + /* 17 - _17 */ 0x2016, + /* 18 - _18 */ 0x2017, + /* 19 - _19 */ 0x2018, + /* 1a - _1A */ 0x2019, + /* 1b - _1B */ 0x201a, + /* 1c - _1C */ 0x201b, + /* 1d - _1D */ 0x201c, + /* 1e - _1E */ 0x201d, + /* 1f - _1F */ 0x201e, + /* 20 - _20 */ 0x201f, + /* 21 - _21 */ 0x2020, + /* 22 - _22 */ 0x2021, + /* 23 - _23 */ 0x2022, + /* 24 - _24 */ 0x2023, + /* 25 - _25 */ 0x2024, + /* 26 - */ 0, + /* 27 - _27 */ 0x2025, + /* 28 - _28 */ 0x2026, + /* 29 - _29 */ 0x2027, + /* 2a - _2A */ 0x2028, + /* 2b - _2B */ 0x2029, + /* 2c - _2C */ 0x202a, + /* 2d - _2D */ 0x202b, + /* 2e - */ 0, + /* 2f - _2F */ 0x202c, + /* 30 - _30 */ 0x202d, + /* 31 - _31 */ 0x202e, + /* 32 - _32 */ 0x202f, + /* 33 - _33 */ 0x2030, + /* 34 - _34 */ 0x2031, + /* 35 - _35 */ 0x2032, + /* 36 - */ 0, + /* 37 - _37 */ 0x2033, + /* 38 - _38 */ 0x2034, + /* 39 - _39 */ 0x2035, + /* 3a - _3A */ 0x2036, + /* 3b - _3B */ 0x2037, + /* 3c - _3C */ 0x2038, + /* 3d - _3D */ 0x2039, + /* 3e - */ 0, + /* 3f - _3F */ 0x203a, + /* 40 - _40 */ 0x203b, + /* 41 - _40 */ 0x203c, + /* 42 - _40 */ 0x203d, + /* 43 - _40 */ 0x203e, + /* 44 - _40 */ 0x203f, + /* 45 - _40 */ 0x2040, + /* 46 - _40 */ 0x2041, + /* 47 - _40 */ 0x2042, + /* 48 - _48 */ 0x2043, + /* 49 - _48 */ 0x2044, + /* 4a - _48 */ 0x2045, + /* 4b - _48 */ 0x2046, + /* 4c - _48 */ 0x2047, + /* 4d - _48 */ 0x2048, + /* 4e - _48 */ 0x2049, + /* 4f - _48 */ 0x204a, + /* 50 - _50 */ 0x204b, + /* 51 - _50 */ 0x204c, + /* 52 - _50 */ 0x204d, + /* 53 - _50 */ 0x204e, + /* 54 - _50 */ 0x204f, + /* 55 - _50 */ 0x2050, + /* 56 - _50 */ 0x2051, + /* 57 - _50 */ 0x2052, + /* 58 - _58 */ 0x2053, + /* 59 - _58 */ 0x2054, + /* 5a - _58 */ 0x2055, + /* 5b - _58 */ 0x2056, + /* 5c - _58 */ 0x2057, + /* 5d - _58 */ 0x2058, + /* 5e - _58 */ 0x2059, + /* 5f - _58 */ 0x205a, + /* 60 - _60 */ 0x205b, + /* 61 - _61 */ 0x205c, + /* 62 - _62 */ 0x205d, + /* 63 - _63 */ 0x205e, + /* 64 - */ 0, + /* 65 - */ 0, + /* 66 - */ 0, + /* 67 - */ 0, + /* 68 - _68 */ 0x205f, + /* 69 - _69 */ 0x4000, + /* 6a - _6A */ 0x2060, + /* 6b - _6B */ 0x4001, + /* 6c - _6C */ 0x2061, + /* 6d - _6D */ 0x2062, + /* 6e - _6E */ 0x2063, + /* 6f - _6F */ 0x2064, + /* 70 - _70 */ 0x2065, + /* 71 - _71 */ 0x2066, + /* 72 - _72 */ 0x2067, + /* 73 - _73 */ 0x2068, + /* 74 - _74 */ 0x2069, + /* 75 - _75 */ 0x206a, + /* 76 - _76 */ 0x206b, + /* 77 - _77 */ 0x206c, + /* 78 - _78 */ 0x206d, + /* 79 - _79 */ 0x206e, + /* 7a - _7A */ 0x206f, + /* 7b - _7B */ 0x2070, + /* 7c - _7C */ 0x2071, + /* 7d - _7D */ 0x2072, + /* 7e - _7E */ 0x2073, + /* 7f - _7F */ 0x2074, + /* 80 - _80 */ 0x6200, + /* 81 - _81 */ 0x6208, + /* 82 - _82 */ 0x6210, + /* 83 - _83 */ 0x6218, + /* 84 - _84 */ 0x2075, + /* 85 - _85 */ 0x2076, + /* 86 - _86 */ 0x2077, + /* 87 - _87 */ 0x2078, + /* 88 - _88 */ 0x2079, + /* 89 - _89 */ 0x207a, + /* 8a - _8A */ 0x207b, + /* 8b - _8B */ 0x207c, + /* 8c - _8C */ 0x207d, + /* 8d - _8D */ 0x207e, + /* 8e - _8E */ 0x207f, + /* 8f - _8F */ 0x6220, + /* 90 - _90 */ 0x2080, + /* 91 - _91 */ 0x2081, + /* 92 - _92 */ 0x2082, + /* 93 - _93 */ 0x2083, + /* 94 - _94 */ 0x2084, + /* 95 - _95 */ 0x2085, + /* 96 - _96 */ 0x2086, + /* 97 - _97 */ 0x2087, + /* 98 - _98 */ 0x4002, + /* 99 - _99 */ 0x4003, + /* 9a - _9A */ 0x2088, + /* 9b - */ 0, + /* 9c - _9C */ 0x2089, + /* 9d - _9D */ 0x208a, + /* 9e - _9E */ 0x208b, + /* 9f - _9F */ 0x208c, + /* a0 - _A0 */ 0x208d, + /* a1 - _A1 */ 0x208e, + /* a2 - _A2 */ 0x208f, + /* a3 - _A3 */ 0x2090, + /* a4 - _A4 */ 0x2091, + /* a5 - _A5 */ 0x2092, + /* a6 - _A6 */ 0x2093, + /* a7 - _A7 */ 0x2094, + /* a8 - _A8 */ 0x2095, + /* a9 - _A9 */ 0x2096, + /* aa - _AA */ 0x2097, + /* ab - _AB */ 0x2098, + /* ac - _AC */ 0x2099, + /* ad - _AD */ 0x209a, + /* ae - _AE */ 0x209b, + /* af - _AF */ 0x209c, + /* b0 - _B0 */ 0x209d, + /* b1 - _B0 */ 0x209e, + /* b2 - _B0 */ 0x209f, + /* b3 - _B0 */ 0x20a0, + /* b4 - _B0 */ 0x20a1, + /* b5 - _B0 */ 0x20a2, + /* b6 - _B0 */ 0x20a3, + /* b7 - _B0 */ 0x20a4, + /* b8 - _B8 */ 0x20a5, + /* b9 - _B8 */ 0x20a6, + /* ba - _B8 */ 0x20a7, + /* bb - _B8 */ 0x20a8, + /* bc - _B8 */ 0x20a9, + /* bd - _B8 */ 0x20aa, + /* be - _B8 */ 0x20ab, + /* bf - _B8 */ 0x20ac, + /* c0 - _C0 */ 0x6228, + /* c1 - _C1 */ 0x6230, + /* c2 - _C2 */ 0x20ad, + /* c3 - _C3 */ 0x20ae, + /* c4 - _C4 */ 0x20af, + /* c5 - _C5 */ 0x20b0, + /* c6 - _C6 */ 0xa238, + /* c7 - _C7 */ 0xa280, + /* c8 - _C8 */ 0x20b1, + /* c9 - _C9 */ 0x20b2, + /* ca - _CA */ 0x20b3, + /* cb - _CB */ 0x20b4, + /* cc - _CC */ 0x20b5, + /* cd - _CD */ 0x20b6, + /* ce - _CE */ 0x20b7, + /* cf - _CF */ 0x20b8, + /* d0 - _D0 */ 0x62c8, + /* d1 - _D1 */ 0x62d0, + /* d2 - _D2 */ 0x62d8, + /* d3 - _D3 */ 0x62e0, + /* d4 - _D4 */ 0x20b9, + /* d5 - _D5 */ 0x20ba, + /* d6 - _D6 */ 0x20bb, + /* d7 - _D7 */ 0x20bc, + /* d8 - _D8 */ 0xa2e8, + /* d9 - _D9 */ 0xa330, + /* da - _DA */ 0xa378, + /* db - _DB */ 0xa3c0, + /* dc - _DC */ 0xa408, + /* dd - _DD */ 0xa450, + /* de - _DE */ 0xa498, + /* df - _DF */ 0xa4e0, + /* e0 - _E0 */ 0x20bd, + /* e1 - _E1 */ 0x20be, + /* e2 - _E2 */ 0x20bf, + /* e3 - _E3 */ 0x4004, + /* e4 - _E4 */ 0x20c0, + /* e5 - _E5 */ 0x20c1, + /* e6 - _E6 */ 0x20c2, + /* e7 - _E7 */ 0x20c3, + /* e8 - _E8 */ 0x20c4, + /* e9 - _E9 */ 0x20c5, + /* ea - _EA */ 0x20c6, + /* eb - _EB */ 0x20c7, + /* ec - _EC */ 0x20c8, + /* ed - _ED */ 0x20c9, + /* ee - _EE */ 0x20ca, + /* ef - _EF */ 0x20cb, + /* f0 - */ 0, + /* f1 - _F1 */ 0x20cc, + /* f2 - */ 0, + /* f3 - */ 0, + /* f4 - _F4 */ 0x20cd, + /* f5 - _F5 */ 0x20ce, + /* f6 - _F6 */ 0x6528, + /* f7 - _F7 */ 0x6530, + /* f8 - _F8 */ 0x20cf, + /* f9 - _F9 */ 0x20d0, + /* fa - _FA */ 0x20d1, + /* fb - _FB */ 0x20d2, + /* fc - _FC */ 0x20d3, + /* fd - _FD */ 0x20d4, + /* fe - _FE */ 0x6538, + /* ff - _FF */ 0x6540, + /* 100 - _0F_00 */ 0x6548, + /* 101 - _0F_01 */ 0xa550, + /* 102 - _0F_02 */ 0x20d5, + /* 103 - _0F_03 */ 0x20d6, + /* 104 - */ 0, + /* 105 - _0F_05 */ 0x20d7, + /* 106 - _0F_06 */ 0x20d8, + /* 107 - _0F_07 */ 0x20d9, + /* 108 - _0F_08 */ 0x20da, + /* 109 - _0F_09 */ 0x20db, + /* 10a - */ 0, + /* 10b - _0F_0B */ 0x20dc, + /* 10c - */ 0, + /* 10d - _0F_0D */ 0x6598, + /* 10e - _0F_0E */ 0x20dd, + /* 10f - _0F_0F */ 0x85a0, + /* 110 - _0F_10 */ 0xc6a0, + /* 111 - _0F_11 */ 0xc6ac, + /* 112 - _0F_12 */ 0xc6b8, + /* 113 - _0F_13 */ 0xc6c4, + /* 114 - _0F_14 */ 0xc6d0, + /* 115 - _0F_15 */ 0xc6dc, + /* 116 - _0F_16 */ 0xc6e8, + /* 117 - _0F_17 */ 0xc6f4, + /* 118 - _0F_18 */ 0x6700, + /* 119 - */ 0, + /* 11a - */ 0, + /* 11b - */ 0, + /* 11c - */ 0, + /* 11d - */ 0, + /* 11e - */ 0, + /* 11f - _0F_1F */ 0x20de, + /* 120 - _0F_20 */ 0x20df, + /* 121 - _0F_21 */ 0x20e0, + /* 122 - _0F_22 */ 0x20e1, + /* 123 - _0F_23 */ 0x20e2, + /* 124 - */ 0, + /* 125 - */ 0, + /* 126 - */ 0, + /* 127 - */ 0, + /* 128 - _0F_28 */ 0xc708, + /* 129 - _0F_29 */ 0xc714, + /* 12a - _0F_2A */ 0xc720, + /* 12b - _0F_2B */ 0xc72c, + /* 12c - _0F_2C */ 0xc738, + /* 12d - _0F_2D */ 0xc744, + /* 12e - _0F_2E */ 0xc750, + /* 12f - _0F_2F */ 0xc75c, + /* 130 - _0F_30 */ 0x20e3, + /* 131 - _0F_31 */ 0x20e4, + /* 132 - _0F_32 */ 0x20e5, + /* 133 - _0F_33 */ 0x20e6, + /* 134 - _0F_34 */ 0x20e7, + /* 135 - _0F_35 */ 0x20e8, + /* 136 - */ 0, + /* 137 - _0F_37 */ 0x20e9, + /* 138 - _0F_38 */ 0x8768, + /* 139 - */ 0, + /* 13a - _0F_3A */ 0x8868, + /* 13b - */ 0, + /* 13c - */ 0, + /* 13d - */ 0, + /* 13e - */ 0, + /* 13f - */ 0, + /* 140 - _0F_40 */ 0x20ea, + /* 141 - _0F_41 */ 0x20eb, + /* 142 - _0F_42 */ 0x20ec, + /* 143 - _0F_43 */ 0x20ed, + /* 144 - _0F_44 */ 0x20ee, + /* 145 - _0F_45 */ 0x20ef, + /* 146 - _0F_46 */ 0x20f0, + /* 147 - _0F_47 */ 0x20f1, + /* 148 - _0F_48 */ 0x20f2, + /* 149 - _0F_49 */ 0x20f3, + /* 14a - _0F_4A */ 0x20f4, + /* 14b - _0F_4B */ 0x20f5, + /* 14c - _0F_4C */ 0x20f6, + /* 14d - _0F_4D */ 0x20f7, + /* 14e - _0F_4E */ 0x20f8, + /* 14f - _0F_4F */ 0x20f9, + /* 150 - _0F_50 */ 0xc968, + /* 151 - _0F_51 */ 0xc974, + /* 152 - _0F_52 */ 0xc980, + /* 153 - _0F_53 */ 0xc98c, + /* 154 - _0F_54 */ 0xc998, + /* 155 - _0F_55 */ 0xc9a4, + /* 156 - _0F_56 */ 0xc9b0, + /* 157 - _0F_57 */ 0xc9bc, + /* 158 - _0F_58 */ 0xc9c8, + /* 159 - _0F_59 */ 0xc9d4, + /* 15a - _0F_5A */ 0xc9e0, + /* 15b - _0F_5B */ 0xc9ec, + /* 15c - _0F_5C */ 0xc9f8, + /* 15d - _0F_5D */ 0xca04, + /* 15e - _0F_5E */ 0xca10, + /* 15f - _0F_5F */ 0xca1c, + /* 160 - _0F_60 */ 0xca28, + /* 161 - _0F_61 */ 0xca34, + /* 162 - _0F_62 */ 0xca40, + /* 163 - _0F_63 */ 0xca4c, + /* 164 - _0F_64 */ 0xca58, + /* 165 - _0F_65 */ 0xca64, + /* 166 - _0F_66 */ 0xca70, + /* 167 - _0F_67 */ 0xca7c, + /* 168 - _0F_68 */ 0xca88, + /* 169 - _0F_69 */ 0xca94, + /* 16a - _0F_6A */ 0xcaa0, + /* 16b - _0F_6B */ 0xcaac, + /* 16c - _0F_6C */ 0xcab8, + /* 16d - _0F_6D */ 0xcac4, + /* 16e - _0F_6E */ 0xcad0, + /* 16f - _0F_6F */ 0xcadc, + /* 170 - _0F_70 */ 0xcae8, + /* 171 - _0F_71 */ 0x6af4, + /* 172 - _0F_72 */ 0x6afc, + /* 173 - _0F_73 */ 0x6b04, + /* 174 - _0F_74 */ 0xcb0c, + /* 175 - _0F_75 */ 0xcb18, + /* 176 - _0F_76 */ 0xcb24, + /* 177 - _0F_77 */ 0xcb30, + /* 178 - _0F_78 */ 0xcb3c, + /* 179 - _0F_79 */ 0xcb48, + /* 17a - _0F_7A */ 0x8b54, + /* 17b - */ 0, + /* 17c - _0F_7C */ 0xcc54, + /* 17d - _0F_7D */ 0xcc60, + /* 17e - _0F_7E */ 0xcc6c, + /* 17f - _0F_7F */ 0xcc78, + /* 180 - _0F_80 */ 0x20fa, + /* 181 - _0F_81 */ 0x20fb, + /* 182 - _0F_82 */ 0x20fc, + /* 183 - _0F_83 */ 0x20fd, + /* 184 - _0F_84 */ 0x20fe, + /* 185 - _0F_85 */ 0x20ff, + /* 186 - _0F_86 */ 0x2100, + /* 187 - _0F_87 */ 0x2101, + /* 188 - _0F_88 */ 0x2102, + /* 189 - _0F_89 */ 0x2103, + /* 18a - _0F_8A */ 0x2104, + /* 18b - _0F_8B */ 0x2105, + /* 18c - _0F_8C */ 0x2106, + /* 18d - _0F_8D */ 0x2107, + /* 18e - _0F_8E */ 0x2108, + /* 18f - _0F_8F */ 0x2109, + /* 190 - _0F_90 */ 0x210a, + /* 191 - _0F_91 */ 0x210b, + /* 192 - _0F_92 */ 0x210c, + /* 193 - _0F_93 */ 0x210d, + /* 194 - _0F_94 */ 0x210e, + /* 195 - _0F_95 */ 0x210f, + /* 196 - _0F_96 */ 0x2110, + /* 197 - _0F_97 */ 0x2111, + /* 198 - _0F_98 */ 0x2112, + /* 199 - _0F_99 */ 0x2113, + /* 19a - _0F_9A */ 0x2114, + /* 19b - _0F_9B */ 0x2115, + /* 19c - _0F_9C */ 0x2116, + /* 19d - _0F_9D */ 0x2117, + /* 19e - _0F_9E */ 0x2118, + /* 19f - _0F_9F */ 0x2119, + /* 1a0 - _0F_A0 */ 0x211a, + /* 1a1 - _0F_A1 */ 0x211b, + /* 1a2 - _0F_A2 */ 0x211c, + /* 1a3 - _0F_A3 */ 0x211d, + /* 1a4 - _0F_A4 */ 0x4005, + /* 1a5 - _0F_A5 */ 0x4006, + /* 1a6 - */ 0, + /* 1a7 - */ 0, + /* 1a8 - _0F_A8 */ 0x211e, + /* 1a9 - _0F_A9 */ 0x211f, + /* 1aa - _0F_AA */ 0x2120, + /* 1ab - _0F_AB */ 0x2121, + /* 1ac - _0F_AC */ 0x4007, + /* 1ad - _0F_AD */ 0x4008, + /* 1ae - _0F_AE */ 0x6c84, + /* 1af - _0F_AF */ 0x2122, + /* 1b0 - _0F_B0 */ 0x2123, + /* 1b1 - _0F_B1 */ 0x2124, + /* 1b2 - _0F_B2 */ 0x2125, + /* 1b3 - _0F_B3 */ 0x2126, + /* 1b4 - _0F_B4 */ 0x2127, + /* 1b5 - _0F_B5 */ 0x2128, + /* 1b6 - _0F_B6 */ 0x2129, + /* 1b7 - _0F_B7 */ 0x212a, + /* 1b8 - _0F_B8 */ 0xcc8c, + /* 1b9 - _0F_B9 */ 0x212b, + /* 1ba - _0F_BA */ 0x6c98, + /* 1bb - _0F_BB */ 0x212c, + /* 1bc - _0F_BC */ 0xcca0, + /* 1bd - _0F_BD */ 0xccac, + /* 1be - _0F_BE */ 0x212d, + /* 1bf - _0F_BF */ 0x212e, + /* 1c0 - _0F_C0 */ 0x212f, + /* 1c1 - _0F_C1 */ 0x2130, + /* 1c2 - _0F_C2 */ 0xccb8, + /* 1c3 - _0F_C3 */ 0x2131, + /* 1c4 - _0F_C4 */ 0xccc4, + /* 1c5 - _0F_C5 */ 0xccd0, + /* 1c6 - _0F_C6 */ 0xccdc, + /* 1c7 - _0F_C7 */ 0x6ce8, + /* 1c8 - _0F_C8 */ 0x2132, + /* 1c9 - _0F_C8 */ 0x2133, + /* 1ca - _0F_C8 */ 0x2134, + /* 1cb - _0F_C8 */ 0x2135, + /* 1cc - _0F_C8 */ 0x2136, + /* 1cd - _0F_C8 */ 0x2137, + /* 1ce - _0F_C8 */ 0x2138, + /* 1cf - _0F_C8 */ 0x2139, + /* 1d0 - _0F_D0 */ 0xccf0, + /* 1d1 - _0F_D1 */ 0xccfc, + /* 1d2 - _0F_D2 */ 0xcd08, + /* 1d3 - _0F_D3 */ 0xcd14, + /* 1d4 - _0F_D4 */ 0xcd20, + /* 1d5 - _0F_D5 */ 0xcd2c, + /* 1d6 - _0F_D6 */ 0xcd38, + /* 1d7 - _0F_D7 */ 0xcd44, + /* 1d8 - _0F_D8 */ 0xcd50, + /* 1d9 - _0F_D9 */ 0xcd5c, + /* 1da - _0F_DA */ 0xcd68, + /* 1db - _0F_DB */ 0xcd74, + /* 1dc - _0F_DC */ 0xcd80, + /* 1dd - _0F_DD */ 0xcd8c, + /* 1de - _0F_DE */ 0xcd98, + /* 1df - _0F_DF */ 0xcda4, + /* 1e0 - _0F_E0 */ 0xcdb0, + /* 1e1 - _0F_E1 */ 0xcdbc, + /* 1e2 - _0F_E2 */ 0xcdc8, + /* 1e3 - _0F_E3 */ 0xcdd4, + /* 1e4 - _0F_E4 */ 0xcde0, + /* 1e5 - _0F_E5 */ 0xcdec, + /* 1e6 - _0F_E6 */ 0xcdf8, + /* 1e7 - _0F_E7 */ 0xce04, + /* 1e8 - _0F_E8 */ 0xce10, + /* 1e9 - _0F_E9 */ 0xce1c, + /* 1ea - _0F_EA */ 0xce28, + /* 1eb - _0F_EB */ 0xce34, + /* 1ec - _0F_EC */ 0xce40, + /* 1ed - _0F_ED */ 0xce4c, + /* 1ee - _0F_EE */ 0xce58, + /* 1ef - _0F_EF */ 0xce64, + /* 1f0 - _0F_F0 */ 0xce70, + /* 1f1 - _0F_F1 */ 0xce7c, + /* 1f2 - _0F_F2 */ 0xce88, + /* 1f3 - _0F_F3 */ 0xce94, + /* 1f4 - _0F_F4 */ 0xcea0, + /* 1f5 - _0F_F5 */ 0xceac, + /* 1f6 - _0F_F6 */ 0xceb8, + /* 1f7 - _0F_F7 */ 0xcec4, + /* 1f8 - _0F_F8 */ 0xced0, + /* 1f9 - _0F_F9 */ 0xcedc, + /* 1fa - _0F_FA */ 0xcee8, + /* 1fb - _0F_FB */ 0xcef4, + /* 1fc - _0F_FC */ 0xcf00, + /* 1fd - _0F_FD */ 0xcf0c, + /* 1fe - _0F_FE */ 0xcf18, + /* 1ff - */ 0, + /* 200 - _80_00 */ 0x213a, + /* 201 - _80_01 */ 0x213b, + /* 202 - _80_02 */ 0x213c, + /* 203 - _80_03 */ 0x213d, + /* 204 - _80_04 */ 0x213e, + /* 205 - _80_05 */ 0x213f, + /* 206 - _80_06 */ 0x2140, + /* 207 - _80_07 */ 0x2141, + /* 208 - _81_00 */ 0x2142, + /* 209 - _81_01 */ 0x2143, + /* 20a - _81_02 */ 0x2144, + /* 20b - _81_03 */ 0x2145, + /* 20c - _81_04 */ 0x2146, + /* 20d - _81_05 */ 0x2147, + /* 20e - _81_06 */ 0x2148, + /* 20f - _81_07 */ 0x2149, + /* 210 - _82_00 */ 0x214a, + /* 211 - _82_01 */ 0x214b, + /* 212 - _82_02 */ 0x214c, + /* 213 - _82_03 */ 0x214d, + /* 214 - _82_04 */ 0x214e, + /* 215 - _82_05 */ 0x214f, + /* 216 - _82_06 */ 0x2150, + /* 217 - _82_07 */ 0x2151, + /* 218 - _83_00 */ 0x2152, + /* 219 - _83_01 */ 0x2153, + /* 21a - _83_02 */ 0x2154, + /* 21b - _83_03 */ 0x2155, + /* 21c - _83_04 */ 0x2156, + /* 21d - _83_05 */ 0x2157, + /* 21e - _83_06 */ 0x2158, + /* 21f - _83_07 */ 0x2159, + /* 220 - _8F_00 */ 0x215a, + /* 221 - */ 0, + /* 222 - */ 0, + /* 223 - */ 0, + /* 224 - */ 0, + /* 225 - */ 0, + /* 226 - */ 0, + /* 227 - */ 0, + /* 228 - _C0_00 */ 0x215b, + /* 229 - _C0_01 */ 0x215c, + /* 22a - _C0_02 */ 0x215d, + /* 22b - _C0_03 */ 0x215e, + /* 22c - _C0_04 */ 0x215f, + /* 22d - _C0_05 */ 0x2160, + /* 22e - _C0_06 */ 0x2161, + /* 22f - _C0_07 */ 0x2162, + /* 230 - _C1_00 */ 0x2163, + /* 231 - _C1_01 */ 0x2164, + /* 232 - _C1_02 */ 0x2165, + /* 233 - _C1_03 */ 0x2166, + /* 234 - _C1_04 */ 0x2167, + /* 235 - _C1_05 */ 0x2168, + /* 236 - _C1_06 */ 0x2169, + /* 237 - _C1_07 */ 0x216a, + /* 238 - _C6_00 */ 0x216b, + /* 239 - */ 0, + /* 23a - */ 0, + /* 23b - */ 0, + /* 23c - */ 0, + /* 23d - */ 0, + /* 23e - */ 0, + /* 23f - */ 0, + /* 240 - */ 0, + /* 241 - */ 0, + /* 242 - */ 0, + /* 243 - */ 0, + /* 244 - */ 0, + /* 245 - */ 0, + /* 246 - */ 0, + /* 247 - */ 0, + /* 248 - */ 0, + /* 249 - */ 0, + /* 24a - */ 0, + /* 24b - */ 0, + /* 24c - */ 0, + /* 24d - */ 0, + /* 24e - */ 0, + /* 24f - */ 0, + /* 250 - */ 0, + /* 251 - */ 0, + /* 252 - */ 0, + /* 253 - */ 0, + /* 254 - */ 0, + /* 255 - */ 0, + /* 256 - */ 0, + /* 257 - */ 0, + /* 258 - */ 0, + /* 259 - */ 0, + /* 25a - */ 0, + /* 25b - */ 0, + /* 25c - */ 0, + /* 25d - */ 0, + /* 25e - */ 0, + /* 25f - */ 0, + /* 260 - */ 0, + /* 261 - */ 0, + /* 262 - */ 0, + /* 263 - */ 0, + /* 264 - */ 0, + /* 265 - */ 0, + /* 266 - */ 0, + /* 267 - */ 0, + /* 268 - */ 0, + /* 269 - */ 0, + /* 26a - */ 0, + /* 26b - */ 0, + /* 26c - */ 0, + /* 26d - */ 0, + /* 26e - */ 0, + /* 26f - */ 0, + /* 270 - */ 0, + /* 271 - */ 0, + /* 272 - */ 0, + /* 273 - */ 0, + /* 274 - */ 0, + /* 275 - */ 0, + /* 276 - */ 0, + /* 277 - */ 0, + /* 278 - _C6_F8 */ 0x216c, + /* 279 - */ 0, + /* 27a - */ 0, + /* 27b - */ 0, + /* 27c - */ 0, + /* 27d - */ 0, + /* 27e - */ 0, + /* 27f - */ 0, + /* 280 - _C7_00 */ 0x216d, + /* 281 - */ 0, + /* 282 - */ 0, + /* 283 - */ 0, + /* 284 - */ 0, + /* 285 - */ 0, + /* 286 - */ 0, + /* 287 - */ 0, + /* 288 - */ 0, + /* 289 - */ 0, + /* 28a - */ 0, + /* 28b - */ 0, + /* 28c - */ 0, + /* 28d - */ 0, + /* 28e - */ 0, + /* 28f - */ 0, + /* 290 - */ 0, + /* 291 - */ 0, + /* 292 - */ 0, + /* 293 - */ 0, + /* 294 - */ 0, + /* 295 - */ 0, + /* 296 - */ 0, + /* 297 - */ 0, + /* 298 - */ 0, + /* 299 - */ 0, + /* 29a - */ 0, + /* 29b - */ 0, + /* 29c - */ 0, + /* 29d - */ 0, + /* 29e - */ 0, + /* 29f - */ 0, + /* 2a0 - */ 0, + /* 2a1 - */ 0, + /* 2a2 - */ 0, + /* 2a3 - */ 0, + /* 2a4 - */ 0, + /* 2a5 - */ 0, + /* 2a6 - */ 0, + /* 2a7 - */ 0, + /* 2a8 - */ 0, + /* 2a9 - */ 0, + /* 2aa - */ 0, + /* 2ab - */ 0, + /* 2ac - */ 0, + /* 2ad - */ 0, + /* 2ae - */ 0, + /* 2af - */ 0, + /* 2b0 - */ 0, + /* 2b1 - */ 0, + /* 2b2 - */ 0, + /* 2b3 - */ 0, + /* 2b4 - */ 0, + /* 2b5 - */ 0, + /* 2b6 - */ 0, + /* 2b7 - */ 0, + /* 2b8 - */ 0, + /* 2b9 - */ 0, + /* 2ba - */ 0, + /* 2bb - */ 0, + /* 2bc - */ 0, + /* 2bd - */ 0, + /* 2be - */ 0, + /* 2bf - */ 0, + /* 2c0 - _C7_F8 */ 0x216e, + /* 2c1 - */ 0, + /* 2c2 - */ 0, + /* 2c3 - */ 0, + /* 2c4 - */ 0, + /* 2c5 - */ 0, + /* 2c6 - */ 0, + /* 2c7 - */ 0, + /* 2c8 - _D0_00 */ 0x216f, + /* 2c9 - _D0_01 */ 0x2170, + /* 2ca - _D0_02 */ 0x2171, + /* 2cb - _D0_03 */ 0x2172, + /* 2cc - _D0_04 */ 0x2173, + /* 2cd - _D0_05 */ 0x2174, + /* 2ce - _D0_06 */ 0x2175, + /* 2cf - _D0_07 */ 0x2176, + /* 2d0 - _D1_00 */ 0x2177, + /* 2d1 - _D1_01 */ 0x2178, + /* 2d2 - _D1_02 */ 0x2179, + /* 2d3 - _D1_03 */ 0x217a, + /* 2d4 - _D1_04 */ 0x217b, + /* 2d5 - _D1_05 */ 0x217c, + /* 2d6 - _D1_06 */ 0x217d, + /* 2d7 - _D1_07 */ 0x217e, + /* 2d8 - _D2_00 */ 0x217f, + /* 2d9 - _D2_01 */ 0x2180, + /* 2da - _D2_02 */ 0x2181, + /* 2db - _D2_03 */ 0x2182, + /* 2dc - _D2_04 */ 0x2183, + /* 2dd - _D2_05 */ 0x2184, + /* 2de - _D2_06 */ 0x2185, + /* 2df - _D2_07 */ 0x2186, + /* 2e0 - _D3_00 */ 0x2187, + /* 2e1 - _D3_01 */ 0x2188, + /* 2e2 - _D3_02 */ 0x2189, + /* 2e3 - _D3_03 */ 0x218a, + /* 2e4 - _D3_04 */ 0x218b, + /* 2e5 - _D3_05 */ 0x218c, + /* 2e6 - _D3_06 */ 0x218d, + /* 2e7 - _D3_07 */ 0x218e, + /* 2e8 - _D8_00 */ 0x218f, + /* 2e9 - _D8_01 */ 0x2190, + /* 2ea - _D8_02 */ 0x2191, + /* 2eb - _D8_03 */ 0x2192, + /* 2ec - _D8_04 */ 0x2193, + /* 2ed - _D8_05 */ 0x2194, + /* 2ee - _D8_06 */ 0x2195, + /* 2ef - _D8_07 */ 0x2196, + /* 2f0 - _D8_C0 */ 0x2197, + /* 2f1 - _D8_C0 */ 0x2198, + /* 2f2 - _D8_C0 */ 0x2199, + /* 2f3 - _D8_C0 */ 0x219a, + /* 2f4 - _D8_C0 */ 0x219b, + /* 2f5 - _D8_C0 */ 0x219c, + /* 2f6 - _D8_C0 */ 0x219d, + /* 2f7 - _D8_C0 */ 0x219e, + /* 2f8 - _D8_C8 */ 0x219f, + /* 2f9 - _D8_C8 */ 0x21a0, + /* 2fa - _D8_C8 */ 0x21a1, + /* 2fb - _D8_C8 */ 0x21a2, + /* 2fc - _D8_C8 */ 0x21a3, + /* 2fd - _D8_C8 */ 0x21a4, + /* 2fe - _D8_C8 */ 0x21a5, + /* 2ff - _D8_C8 */ 0x21a6, + /* 300 - _D8_D0 */ 0x21a7, + /* 301 - _D8_D0 */ 0x21a8, + /* 302 - _D8_D0 */ 0x21a9, + /* 303 - _D8_D0 */ 0x21aa, + /* 304 - _D8_D0 */ 0x21ab, + /* 305 - _D8_D0 */ 0x21ac, + /* 306 - _D8_D0 */ 0x21ad, + /* 307 - _D8_D0 */ 0x21ae, + /* 308 - _D8_D8 */ 0x21af, + /* 309 - _D8_D9 */ 0x21b0, + /* 30a - _D8_D8 */ 0x21b1, + /* 30b - _D8_D8 */ 0x21b2, + /* 30c - _D8_D8 */ 0x21b3, + /* 30d - _D8_D8 */ 0x21b4, + /* 30e - _D8_D8 */ 0x21b5, + /* 30f - _D8_D8 */ 0x21b6, + /* 310 - _D8_E0 */ 0x21b7, + /* 311 - _D8_E0 */ 0x21b8, + /* 312 - _D8_E0 */ 0x21b9, + /* 313 - _D8_E0 */ 0x21ba, + /* 314 - _D8_E0 */ 0x21bb, + /* 315 - _D8_E0 */ 0x21bc, + /* 316 - _D8_E0 */ 0x21bd, + /* 317 - _D8_E0 */ 0x21be, + /* 318 - _D8_E8 */ 0x21bf, + /* 319 - _D8_E8 */ 0x21c0, + /* 31a - _D8_E8 */ 0x21c1, + /* 31b - _D8_E8 */ 0x21c2, + /* 31c - _D8_E8 */ 0x21c3, + /* 31d - _D8_E8 */ 0x21c4, + /* 31e - _D8_E8 */ 0x21c5, + /* 31f - _D8_E8 */ 0x21c6, + /* 320 - _D8_F0 */ 0x21c7, + /* 321 - _D8_F0 */ 0x21c8, + /* 322 - _D8_F0 */ 0x21c9, + /* 323 - _D8_F0 */ 0x21ca, + /* 324 - _D8_F0 */ 0x21cb, + /* 325 - _D8_F0 */ 0x21cc, + /* 326 - _D8_F0 */ 0x21cd, + /* 327 - _D8_F0 */ 0x21ce, + /* 328 - _D8_F8 */ 0x21cf, + /* 329 - _D8_F8 */ 0x21d0, + /* 32a - _D8_F8 */ 0x21d1, + /* 32b - _D8_F8 */ 0x21d2, + /* 32c - _D8_F8 */ 0x21d3, + /* 32d - _D8_F8 */ 0x21d4, + /* 32e - _D8_F8 */ 0x21d5, + /* 32f - _D8_F8 */ 0x21d6, + /* 330 - _D9_00 */ 0x21d7, + /* 331 - */ 0, + /* 332 - _D9_02 */ 0x21d8, + /* 333 - _D9_03 */ 0x21d9, + /* 334 - _D9_04 */ 0x21da, + /* 335 - _D9_05 */ 0x21db, + /* 336 - _D9_06 */ 0xcf24, + /* 337 - _D9_07 */ 0xcf30, + /* 338 - _D9_C0 */ 0x21dc, + /* 339 - _D9_C0 */ 0x21dd, + /* 33a - _D9_C0 */ 0x21de, + /* 33b - _D9_C0 */ 0x21df, + /* 33c - _D9_C0 */ 0x21e0, + /* 33d - _D9_C0 */ 0x21e1, + /* 33e - _D9_C0 */ 0x21e2, + /* 33f - _D9_C0 */ 0x21e3, + /* 340 - _D9_C8 */ 0x21e4, + /* 341 - _D9_C9 */ 0x21e5, + /* 342 - _D9_C8 */ 0x21e6, + /* 343 - _D9_C8 */ 0x21e7, + /* 344 - _D9_C8 */ 0x21e8, + /* 345 - _D9_C8 */ 0x21e9, + /* 346 - _D9_C8 */ 0x21ea, + /* 347 - _D9_C8 */ 0x21eb, + /* 348 - _D9_D0 */ 0x21ec, + /* 349 - */ 0, + /* 34a - */ 0, + /* 34b - */ 0, + /* 34c - */ 0, + /* 34d - */ 0, + /* 34e - */ 0, + /* 34f - */ 0, + /* 350 - */ 0, + /* 351 - */ 0, + /* 352 - */ 0, + /* 353 - */ 0, + /* 354 - */ 0, + /* 355 - */ 0, + /* 356 - */ 0, + /* 357 - */ 0, + /* 358 - _D9_E0 */ 0x21ed, + /* 359 - _D9_E1 */ 0x21ee, + /* 35a - */ 0, + /* 35b - */ 0, + /* 35c - _D9_E4 */ 0x21ef, + /* 35d - _D9_E5 */ 0x21f0, + /* 35e - */ 0, + /* 35f - */ 0, + /* 360 - _D9_E8 */ 0x21f1, + /* 361 - _D9_E9 */ 0x21f2, + /* 362 - _D9_EA */ 0x21f3, + /* 363 - _D9_EB */ 0x21f4, + /* 364 - _D9_EC */ 0x21f5, + /* 365 - _D9_ED */ 0x21f6, + /* 366 - _D9_EE */ 0x21f7, + /* 367 - */ 0, + /* 368 - _D9_F0 */ 0x21f8, + /* 369 - _D9_F1 */ 0x21f9, + /* 36a - _D9_F2 */ 0x21fa, + /* 36b - _D9_F3 */ 0x21fb, + /* 36c - _D9_F4 */ 0x21fc, + /* 36d - _D9_F5 */ 0x21fd, + /* 36e - _D9_F6 */ 0x21fe, + /* 36f - _D9_F7 */ 0x21ff, + /* 370 - _D9_F8 */ 0x2200, + /* 371 - _D9_F9 */ 0x2201, + /* 372 - _D9_FA */ 0x2202, + /* 373 - _D9_FB */ 0x2203, + /* 374 - _D9_FC */ 0x2204, + /* 375 - _D9_FD */ 0x2205, + /* 376 - _D9_FE */ 0x2206, + /* 377 - _D9_FF */ 0x2207, + /* 378 - _DA_00 */ 0x2208, + /* 379 - _DA_01 */ 0x2209, + /* 37a - _DA_02 */ 0x220a, + /* 37b - _DA_03 */ 0x220b, + /* 37c - _DA_04 */ 0x220c, + /* 37d - _DA_05 */ 0x220d, + /* 37e - _DA_06 */ 0x220e, + /* 37f - _DA_07 */ 0x220f, + /* 380 - _DA_C0 */ 0x2210, + /* 381 - _DA_C0 */ 0x2211, + /* 382 - _DA_C0 */ 0x2212, + /* 383 - _DA_C0 */ 0x2213, + /* 384 - _DA_C0 */ 0x2214, + /* 385 - _DA_C0 */ 0x2215, + /* 386 - _DA_C0 */ 0x2216, + /* 387 - _DA_C0 */ 0x2217, + /* 388 - _DA_C8 */ 0x2218, + /* 389 - _DA_C8 */ 0x2219, + /* 38a - _DA_C8 */ 0x221a, + /* 38b - _DA_C8 */ 0x221b, + /* 38c - _DA_C8 */ 0x221c, + /* 38d - _DA_C8 */ 0x221d, + /* 38e - _DA_C8 */ 0x221e, + /* 38f - _DA_C8 */ 0x221f, + /* 390 - _DA_D0 */ 0x2220, + /* 391 - _DA_D0 */ 0x2221, + /* 392 - _DA_D0 */ 0x2222, + /* 393 - _DA_D0 */ 0x2223, + /* 394 - _DA_D0 */ 0x2224, + /* 395 - _DA_D0 */ 0x2225, + /* 396 - _DA_D0 */ 0x2226, + /* 397 - _DA_D0 */ 0x2227, + /* 398 - _DA_D8 */ 0x2228, + /* 399 - _DA_D8 */ 0x2229, + /* 39a - _DA_D8 */ 0x222a, + /* 39b - _DA_D8 */ 0x222b, + /* 39c - _DA_D8 */ 0x222c, + /* 39d - _DA_D8 */ 0x222d, + /* 39e - _DA_D8 */ 0x222e, + /* 39f - _DA_D8 */ 0x222f, + /* 3a0 - */ 0, + /* 3a1 - */ 0, + /* 3a2 - */ 0, + /* 3a3 - */ 0, + /* 3a4 - */ 0, + /* 3a5 - */ 0, + /* 3a6 - */ 0, + /* 3a7 - */ 0, + /* 3a8 - */ 0, + /* 3a9 - _DA_E9 */ 0x2230, + /* 3aa - */ 0, + /* 3ab - */ 0, + /* 3ac - */ 0, + /* 3ad - */ 0, + /* 3ae - */ 0, + /* 3af - */ 0, + /* 3b0 - */ 0, + /* 3b1 - */ 0, + /* 3b2 - */ 0, + /* 3b3 - */ 0, + /* 3b4 - */ 0, + /* 3b5 - */ 0, + /* 3b6 - */ 0, + /* 3b7 - */ 0, + /* 3b8 - */ 0, + /* 3b9 - */ 0, + /* 3ba - */ 0, + /* 3bb - */ 0, + /* 3bc - */ 0, + /* 3bd - */ 0, + /* 3be - */ 0, + /* 3bf - */ 0, + /* 3c0 - _DB_00 */ 0x2231, + /* 3c1 - _DB_01 */ 0x2232, + /* 3c2 - _DB_02 */ 0x2233, + /* 3c3 - _DB_03 */ 0x2234, + /* 3c4 - */ 0, + /* 3c5 - _DB_05 */ 0x2235, + /* 3c6 - */ 0, + /* 3c7 - _DB_07 */ 0x2236, + /* 3c8 - _DB_C0 */ 0x2237, + /* 3c9 - _DB_C0 */ 0x2238, + /* 3ca - _DB_C0 */ 0x2239, + /* 3cb - _DB_C0 */ 0x223a, + /* 3cc - _DB_C0 */ 0x223b, + /* 3cd - _DB_C0 */ 0x223c, + /* 3ce - _DB_C0 */ 0x223d, + /* 3cf - _DB_C0 */ 0x223e, + /* 3d0 - _DB_C8 */ 0x223f, + /* 3d1 - _DB_C8 */ 0x2240, + /* 3d2 - _DB_C8 */ 0x2241, + /* 3d3 - _DB_C8 */ 0x2242, + /* 3d4 - _DB_C8 */ 0x2243, + /* 3d5 - _DB_C8 */ 0x2244, + /* 3d6 - _DB_C8 */ 0x2245, + /* 3d7 - _DB_C8 */ 0x2246, + /* 3d8 - _DB_D0 */ 0x2247, + /* 3d9 - _DB_D0 */ 0x2248, + /* 3da - _DB_D0 */ 0x2249, + /* 3db - _DB_D0 */ 0x224a, + /* 3dc - _DB_D0 */ 0x224b, + /* 3dd - _DB_D0 */ 0x224c, + /* 3de - _DB_D0 */ 0x224d, + /* 3df - _DB_D0 */ 0x224e, + /* 3e0 - _DB_D8 */ 0x224f, + /* 3e1 - _DB_D8 */ 0x2250, + /* 3e2 - _DB_D8 */ 0x2251, + /* 3e3 - _DB_D8 */ 0x2252, + /* 3e4 - _DB_D8 */ 0x2253, + /* 3e5 - _DB_D8 */ 0x2254, + /* 3e6 - _DB_D8 */ 0x2255, + /* 3e7 - _DB_D8 */ 0x2256, + /* 3e8 - _DB_E0 */ 0x2257, + /* 3e9 - _DB_E1 */ 0x2258, + /* 3ea - _DB_E2 */ 0xcf3c, + /* 3eb - _DB_E3 */ 0xcf48, + /* 3ec - _DB_E4 */ 0x2259, + /* 3ed - */ 0, + /* 3ee - */ 0, + /* 3ef - */ 0, + /* 3f0 - _DB_E8 */ 0x225a, + /* 3f1 - _DB_E8 */ 0x225b, + /* 3f2 - _DB_E8 */ 0x225c, + /* 3f3 - _DB_E8 */ 0x225d, + /* 3f4 - _DB_E8 */ 0x225e, + /* 3f5 - _DB_E8 */ 0x225f, + /* 3f6 - _DB_E8 */ 0x2260, + /* 3f7 - _DB_E8 */ 0x2261, + /* 3f8 - _DB_F0 */ 0x2262, + /* 3f9 - _DB_F0 */ 0x2263, + /* 3fa - _DB_F0 */ 0x2264, + /* 3fb - _DB_F0 */ 0x2265, + /* 3fc - _DB_F0 */ 0x2266, + /* 3fd - _DB_F0 */ 0x2267, + /* 3fe - _DB_F0 */ 0x2268, + /* 3ff - _DB_F0 */ 0x2269, + /* 400 - */ 0, + /* 401 - */ 0, + /* 402 - */ 0, + /* 403 - */ 0, + /* 404 - */ 0, + /* 405 - */ 0, + /* 406 - */ 0, + /* 407 - */ 0, + /* 408 - _DC_00 */ 0x226a, + /* 409 - _DC_01 */ 0x226b, + /* 40a - _DC_02 */ 0x226c, + /* 40b - _DC_03 */ 0x226d, + /* 40c - _DC_04 */ 0x226e, + /* 40d - _DC_05 */ 0x226f, + /* 40e - _DC_06 */ 0x2270, + /* 40f - _DC_07 */ 0x2271, + /* 410 - _DC_C0 */ 0x2272, + /* 411 - _DC_C0 */ 0x2273, + /* 412 - _DC_C0 */ 0x2274, + /* 413 - _DC_C0 */ 0x2275, + /* 414 - _DC_C0 */ 0x2276, + /* 415 - _DC_C0 */ 0x2277, + /* 416 - _DC_C0 */ 0x2278, + /* 417 - _DC_C0 */ 0x2279, + /* 418 - _DC_C8 */ 0x227a, + /* 419 - _DC_C8 */ 0x227b, + /* 41a - _DC_C8 */ 0x227c, + /* 41b - _DC_C8 */ 0x227d, + /* 41c - _DC_C8 */ 0x227e, + /* 41d - _DC_C8 */ 0x227f, + /* 41e - _DC_C8 */ 0x2280, + /* 41f - _DC_C8 */ 0x2281, + /* 420 - */ 0, + /* 421 - */ 0, + /* 422 - */ 0, + /* 423 - */ 0, + /* 424 - */ 0, + /* 425 - */ 0, + /* 426 - */ 0, + /* 427 - */ 0, + /* 428 - */ 0, + /* 429 - */ 0, + /* 42a - */ 0, + /* 42b - */ 0, + /* 42c - */ 0, + /* 42d - */ 0, + /* 42e - */ 0, + /* 42f - */ 0, + /* 430 - _DC_E0 */ 0x2282, + /* 431 - _DC_E0 */ 0x2283, + /* 432 - _DC_E0 */ 0x2284, + /* 433 - _DC_E0 */ 0x2285, + /* 434 - _DC_E0 */ 0x2286, + /* 435 - _DC_E0 */ 0x2287, + /* 436 - _DC_E0 */ 0x2288, + /* 437 - _DC_E0 */ 0x2289, + /* 438 - _DC_E8 */ 0x228a, + /* 439 - _DC_E8 */ 0x228b, + /* 43a - _DC_E8 */ 0x228c, + /* 43b - _DC_E8 */ 0x228d, + /* 43c - _DC_E8 */ 0x228e, + /* 43d - _DC_E8 */ 0x228f, + /* 43e - _DC_E8 */ 0x2290, + /* 43f - _DC_E8 */ 0x2291, + /* 440 - _DC_F0 */ 0x2292, + /* 441 - _DC_F0 */ 0x2293, + /* 442 - _DC_F0 */ 0x2294, + /* 443 - _DC_F0 */ 0x2295, + /* 444 - _DC_F0 */ 0x2296, + /* 445 - _DC_F0 */ 0x2297, + /* 446 - _DC_F0 */ 0x2298, + /* 447 - _DC_F0 */ 0x2299, + /* 448 - _DC_F8 */ 0x229a, + /* 449 - _DC_F8 */ 0x229b, + /* 44a - _DC_F8 */ 0x229c, + /* 44b - _DC_F8 */ 0x229d, + /* 44c - _DC_F8 */ 0x229e, + /* 44d - _DC_F8 */ 0x229f, + /* 44e - _DC_F8 */ 0x22a0, + /* 44f - _DC_F8 */ 0x22a1, + /* 450 - _DD_00 */ 0x22a2, + /* 451 - _DD_01 */ 0x22a3, + /* 452 - _DD_02 */ 0x22a4, + /* 453 - _DD_03 */ 0x22a5, + /* 454 - _DD_04 */ 0x22a6, + /* 455 - */ 0, + /* 456 - _DD_06 */ 0xcf54, + /* 457 - _DD_07 */ 0xcf60, + /* 458 - _DD_C0 */ 0x22a7, + /* 459 - _DD_C0 */ 0x22a8, + /* 45a - _DD_C0 */ 0x22a9, + /* 45b - _DD_C0 */ 0x22aa, + /* 45c - _DD_C0 */ 0x22ab, + /* 45d - _DD_C0 */ 0x22ac, + /* 45e - _DD_C0 */ 0x22ad, + /* 45f - _DD_C0 */ 0x22ae, + /* 460 - */ 0, + /* 461 - */ 0, + /* 462 - */ 0, + /* 463 - */ 0, + /* 464 - */ 0, + /* 465 - */ 0, + /* 466 - */ 0, + /* 467 - */ 0, + /* 468 - _DD_D0 */ 0x22af, + /* 469 - _DD_D0 */ 0x22b0, + /* 46a - _DD_D0 */ 0x22b1, + /* 46b - _DD_D0 */ 0x22b2, + /* 46c - _DD_D0 */ 0x22b3, + /* 46d - _DD_D0 */ 0x22b4, + /* 46e - _DD_D0 */ 0x22b5, + /* 46f - _DD_D0 */ 0x22b6, + /* 470 - _DD_D8 */ 0x22b7, + /* 471 - _DD_D8 */ 0x22b8, + /* 472 - _DD_D8 */ 0x22b9, + /* 473 - _DD_D8 */ 0x22ba, + /* 474 - _DD_D8 */ 0x22bb, + /* 475 - _DD_D8 */ 0x22bc, + /* 476 - _DD_D8 */ 0x22bd, + /* 477 - _DD_D8 */ 0x22be, + /* 478 - _DD_E0 */ 0x22bf, + /* 479 - _DD_E1 */ 0x22c0, + /* 47a - _DD_E0 */ 0x22c1, + /* 47b - _DD_E0 */ 0x22c2, + /* 47c - _DD_E0 */ 0x22c3, + /* 47d - _DD_E0 */ 0x22c4, + /* 47e - _DD_E0 */ 0x22c5, + /* 47f - _DD_E0 */ 0x22c6, + /* 480 - _DD_E8 */ 0x22c7, + /* 481 - _DD_E9 */ 0x22c8, + /* 482 - _DD_E8 */ 0x22c9, + /* 483 - _DD_E8 */ 0x22ca, + /* 484 - _DD_E8 */ 0x22cb, + /* 485 - _DD_E8 */ 0x22cc, + /* 486 - _DD_E8 */ 0x22cd, + /* 487 - _DD_E8 */ 0x22ce, + /* 488 - */ 0, + /* 489 - */ 0, + /* 48a - */ 0, + /* 48b - */ 0, + /* 48c - */ 0, + /* 48d - */ 0, + /* 48e - */ 0, + /* 48f - */ 0, + /* 490 - */ 0, + /* 491 - */ 0, + /* 492 - */ 0, + /* 493 - */ 0, + /* 494 - */ 0, + /* 495 - */ 0, + /* 496 - */ 0, + /* 497 - */ 0, + /* 498 - _DE_00 */ 0x22cf, + /* 499 - _DE_01 */ 0x22d0, + /* 49a - _DE_02 */ 0x22d1, + /* 49b - _DE_03 */ 0x22d2, + /* 49c - _DE_04 */ 0x22d3, + /* 49d - _DE_05 */ 0x22d4, + /* 49e - _DE_06 */ 0x22d5, + /* 49f - _DE_07 */ 0x22d6, + /* 4a0 - _DE_C0 */ 0x22d7, + /* 4a1 - _DE_C1 */ 0x22d8, + /* 4a2 - _DE_C0 */ 0x22d9, + /* 4a3 - _DE_C0 */ 0x22da, + /* 4a4 - _DE_C0 */ 0x22db, + /* 4a5 - _DE_C0 */ 0x22dc, + /* 4a6 - _DE_C0 */ 0x22dd, + /* 4a7 - _DE_C0 */ 0x22de, + /* 4a8 - _DE_C8 */ 0x22df, + /* 4a9 - _DE_C9 */ 0x22e0, + /* 4aa - _DE_C8 */ 0x22e1, + /* 4ab - _DE_C8 */ 0x22e2, + /* 4ac - _DE_C8 */ 0x22e3, + /* 4ad - _DE_C8 */ 0x22e4, + /* 4ae - _DE_C8 */ 0x22e5, + /* 4af - _DE_C8 */ 0x22e6, + /* 4b0 - */ 0, + /* 4b1 - */ 0, + /* 4b2 - */ 0, + /* 4b3 - */ 0, + /* 4b4 - */ 0, + /* 4b5 - */ 0, + /* 4b6 - */ 0, + /* 4b7 - */ 0, + /* 4b8 - */ 0, + /* 4b9 - _DE_D9 */ 0x22e7, + /* 4ba - */ 0, + /* 4bb - */ 0, + /* 4bc - */ 0, + /* 4bd - */ 0, + /* 4be - */ 0, + /* 4bf - */ 0, + /* 4c0 - _DE_E0 */ 0x22e8, + /* 4c1 - _DE_E1 */ 0x22e9, + /* 4c2 - _DE_E0 */ 0x22ea, + /* 4c3 - _DE_E0 */ 0x22eb, + /* 4c4 - _DE_E0 */ 0x22ec, + /* 4c5 - _DE_E0 */ 0x22ed, + /* 4c6 - _DE_E0 */ 0x22ee, + /* 4c7 - _DE_E0 */ 0x22ef, + /* 4c8 - _DE_E8 */ 0x22f0, + /* 4c9 - _DE_E9 */ 0x22f1, + /* 4ca - _DE_E8 */ 0x22f2, + /* 4cb - _DE_E8 */ 0x22f3, + /* 4cc - _DE_E8 */ 0x22f4, + /* 4cd - _DE_E8 */ 0x22f5, + /* 4ce - _DE_E8 */ 0x22f6, + /* 4cf - _DE_E8 */ 0x22f7, + /* 4d0 - _DE_F0 */ 0x22f8, + /* 4d1 - _DE_F1 */ 0x22f9, + /* 4d2 - _DE_F0 */ 0x22fa, + /* 4d3 - _DE_F0 */ 0x22fb, + /* 4d4 - _DE_F0 */ 0x22fc, + /* 4d5 - _DE_F0 */ 0x22fd, + /* 4d6 - _DE_F0 */ 0x22fe, + /* 4d7 - _DE_F0 */ 0x22ff, + /* 4d8 - _DE_F8 */ 0x2300, + /* 4d9 - _DE_F9 */ 0x2301, + /* 4da - _DE_F8 */ 0x2302, + /* 4db - _DE_F8 */ 0x2303, + /* 4dc - _DE_F8 */ 0x2304, + /* 4dd - _DE_F8 */ 0x2305, + /* 4de - _DE_F8 */ 0x2306, + /* 4df - _DE_F8 */ 0x2307, + /* 4e0 - _DF_00 */ 0x2308, + /* 4e1 - _DF_01 */ 0x2309, + /* 4e2 - _DF_02 */ 0x230a, + /* 4e3 - _DF_03 */ 0x230b, + /* 4e4 - _DF_04 */ 0x230c, + /* 4e5 - _DF_05 */ 0x230d, + /* 4e6 - _DF_06 */ 0x230e, + /* 4e7 - _DF_07 */ 0x230f, + /* 4e8 - */ 0, + /* 4e9 - */ 0, + /* 4ea - */ 0, + /* 4eb - */ 0, + /* 4ec - */ 0, + /* 4ed - */ 0, + /* 4ee - */ 0, + /* 4ef - */ 0, + /* 4f0 - */ 0, + /* 4f1 - */ 0, + /* 4f2 - */ 0, + /* 4f3 - */ 0, + /* 4f4 - */ 0, + /* 4f5 - */ 0, + /* 4f6 - */ 0, + /* 4f7 - */ 0, + /* 4f8 - */ 0, + /* 4f9 - */ 0, + /* 4fa - */ 0, + /* 4fb - */ 0, + /* 4fc - */ 0, + /* 4fd - */ 0, + /* 4fe - */ 0, + /* 4ff - */ 0, + /* 500 - */ 0, + /* 501 - */ 0, + /* 502 - */ 0, + /* 503 - */ 0, + /* 504 - */ 0, + /* 505 - */ 0, + /* 506 - */ 0, + /* 507 - */ 0, + /* 508 - _DF_E0 */ 0xcf6c, + /* 509 - */ 0, + /* 50a - */ 0, + /* 50b - */ 0, + /* 50c - */ 0, + /* 50d - */ 0, + /* 50e - */ 0, + /* 50f - */ 0, + /* 510 - _DF_E8 */ 0x2310, + /* 511 - _DF_E8 */ 0x2311, + /* 512 - _DF_E8 */ 0x2312, + /* 513 - _DF_E8 */ 0x2313, + /* 514 - _DF_E8 */ 0x2314, + /* 515 - _DF_E8 */ 0x2315, + /* 516 - _DF_E8 */ 0x2316, + /* 517 - _DF_E8 */ 0x2317, + /* 518 - _DF_F0 */ 0x2318, + /* 519 - _DF_F0 */ 0x2319, + /* 51a - _DF_F0 */ 0x231a, + /* 51b - _DF_F0 */ 0x231b, + /* 51c - _DF_F0 */ 0x231c, + /* 51d - _DF_F0 */ 0x231d, + /* 51e - _DF_F0 */ 0x231e, + /* 51f - _DF_F0 */ 0x231f, + /* 520 - */ 0, + /* 521 - */ 0, + /* 522 - */ 0, + /* 523 - */ 0, + /* 524 - */ 0, + /* 525 - */ 0, + /* 526 - */ 0, + /* 527 - */ 0, + /* 528 - _F6_00 */ 0x2320, + /* 529 - */ 0, + /* 52a - _F6_02 */ 0x2321, + /* 52b - _F6_03 */ 0x2322, + /* 52c - _F6_04 */ 0x2323, + /* 52d - _F6_05 */ 0x2324, + /* 52e - _F6_06 */ 0x2325, + /* 52f - _F6_07 */ 0x2326, + /* 530 - _F7_00 */ 0x2327, + /* 531 - */ 0, + /* 532 - _F7_02 */ 0x2328, + /* 533 - _F7_03 */ 0x2329, + /* 534 - _F7_04 */ 0x232a, + /* 535 - _F7_05 */ 0x232b, + /* 536 - _F7_06 */ 0x232c, + /* 537 - _F7_07 */ 0x232d, + /* 538 - _FE_00 */ 0x232e, + /* 539 - _FE_01 */ 0x232f, + /* 53a - */ 0, + /* 53b - */ 0, + /* 53c - */ 0, + /* 53d - */ 0, + /* 53e - */ 0, + /* 53f - */ 0, + /* 540 - _FF_00 */ 0x2330, + /* 541 - _FF_01 */ 0x2331, + /* 542 - _FF_02 */ 0x2332, + /* 543 - _FF_03 */ 0x2333, + /* 544 - _FF_04 */ 0x2334, + /* 545 - _FF_05 */ 0x2335, + /* 546 - _FF_06 */ 0x2336, + /* 547 - */ 0, + /* 548 - _0F_00_00 */ 0x2337, + /* 549 - _0F_00_01 */ 0x2338, + /* 54a - _0F_00_02 */ 0x2339, + /* 54b - _0F_00_03 */ 0x233a, + /* 54c - _0F_00_04 */ 0x233b, + /* 54d - _0F_00_05 */ 0x233c, + /* 54e - */ 0, + /* 54f - */ 0, + /* 550 - _0F_01_00 */ 0x233d, + /* 551 - _0F_01_01 */ 0x233e, + /* 552 - _0F_01_02 */ 0x233f, + /* 553 - _0F_01_03 */ 0x2340, + /* 554 - _0F_01_04 */ 0x2341, + /* 555 - */ 0, + /* 556 - _0F_01_06 */ 0x2342, + /* 557 - _0F_01_07 */ 0x2343, + /* 558 - */ 0, + /* 559 - _0F_01_C1 */ 0x2344, + /* 55a - _0F_01_C2 */ 0x2345, + /* 55b - _0F_01_C3 */ 0x2346, + /* 55c - _0F_01_C4 */ 0x2347, + /* 55d - */ 0, + /* 55e - */ 0, + /* 55f - */ 0, + /* 560 - _0F_01_C8 */ 0x2348, + /* 561 - _0F_01_C9 */ 0x2349, + /* 562 - */ 0, + /* 563 - */ 0, + /* 564 - */ 0, + /* 565 - */ 0, + /* 566 - */ 0, + /* 567 - */ 0, + /* 568 - _0F_01_D0 */ 0x234a, + /* 569 - _0F_01_D1 */ 0x234b, + /* 56a - */ 0, + /* 56b - */ 0, + /* 56c - _0F_01_D4 */ 0x234c, + /* 56d - _0F_01_D5 */ 0x234d, + /* 56e - */ 0, + /* 56f - */ 0, + /* 570 - _0F_01_D8 */ 0x234e, + /* 571 - _0F_01_D9 */ 0x234f, + /* 572 - _0F_01_DA */ 0x2350, + /* 573 - _0F_01_DB */ 0x2351, + /* 574 - _0F_01_DC */ 0x2352, + /* 575 - _0F_01_DD */ 0x2353, + /* 576 - _0F_01_DE */ 0x2354, + /* 577 - _0F_01_DF */ 0x2355, + /* 578 - */ 0, + /* 579 - */ 0, + /* 57a - */ 0, + /* 57b - */ 0, + /* 57c - */ 0, + /* 57d - */ 0, + /* 57e - */ 0, + /* 57f - */ 0, + /* 580 - */ 0, + /* 581 - */ 0, + /* 582 - */ 0, + /* 583 - */ 0, + /* 584 - */ 0, + /* 585 - */ 0, + /* 586 - */ 0, + /* 587 - */ 0, + /* 588 - */ 0, + /* 589 - */ 0, + /* 58a - */ 0, + /* 58b - */ 0, + /* 58c - */ 0, + /* 58d - */ 0, + /* 58e - */ 0, + /* 58f - */ 0, + /* 590 - _0F_01_F8 */ 0x2356, + /* 591 - _0F_01_F9 */ 0x2357, + /* 592 - */ 0, + /* 593 - */ 0, + /* 594 - */ 0, + /* 595 - */ 0, + /* 596 - */ 0, + /* 597 - */ 0, + /* 598 - _0F_0D_00 */ 0x2358, + /* 599 - _0F_0D_01 */ 0x2359, + /* 59a - */ 0, + /* 59b - */ 0, + /* 59c - */ 0, + /* 59d - */ 0, + /* 59e - */ 0, + /* 59f - */ 0, + /* 5a0 - */ 0, + /* 5a1 - */ 0, + /* 5a2 - */ 0, + /* 5a3 - */ 0, + /* 5a4 - */ 0, + /* 5a5 - */ 0, + /* 5a6 - */ 0, + /* 5a7 - */ 0, + /* 5a8 - */ 0, + /* 5a9 - */ 0, + /* 5aa - */ 0, + /* 5ab - */ 0, + /* 5ac - _0F_0F_0C */ 0x235a, + /* 5ad - _0F_0F_0D */ 0x235b, + /* 5ae - */ 0, + /* 5af - */ 0, + /* 5b0 - */ 0, + /* 5b1 - */ 0, + /* 5b2 - */ 0, + /* 5b3 - */ 0, + /* 5b4 - */ 0, + /* 5b5 - */ 0, + /* 5b6 - */ 0, + /* 5b7 - */ 0, + /* 5b8 - */ 0, + /* 5b9 - */ 0, + /* 5ba - */ 0, + /* 5bb - */ 0, + /* 5bc - _0F_0F_1C */ 0x235c, + /* 5bd - _0F_0F_1D */ 0x235d, + /* 5be - */ 0, + /* 5bf - */ 0, + /* 5c0 - */ 0, + /* 5c1 - */ 0, + /* 5c2 - */ 0, + /* 5c3 - */ 0, + /* 5c4 - */ 0, + /* 5c5 - */ 0, + /* 5c6 - */ 0, + /* 5c7 - */ 0, + /* 5c8 - */ 0, + /* 5c9 - */ 0, + /* 5ca - */ 0, + /* 5cb - */ 0, + /* 5cc - */ 0, + /* 5cd - */ 0, + /* 5ce - */ 0, + /* 5cf - */ 0, + /* 5d0 - */ 0, + /* 5d1 - */ 0, + /* 5d2 - */ 0, + /* 5d3 - */ 0, + /* 5d4 - */ 0, + /* 5d5 - */ 0, + /* 5d6 - */ 0, + /* 5d7 - */ 0, + /* 5d8 - */ 0, + /* 5d9 - */ 0, + /* 5da - */ 0, + /* 5db - */ 0, + /* 5dc - */ 0, + /* 5dd - */ 0, + /* 5de - */ 0, + /* 5df - */ 0, + /* 5e0 - */ 0, + /* 5e1 - */ 0, + /* 5e2 - */ 0, + /* 5e3 - */ 0, + /* 5e4 - */ 0, + /* 5e5 - */ 0, + /* 5e6 - */ 0, + /* 5e7 - */ 0, + /* 5e8 - */ 0, + /* 5e9 - */ 0, + /* 5ea - */ 0, + /* 5eb - */ 0, + /* 5ec - */ 0, + /* 5ed - */ 0, + /* 5ee - */ 0, + /* 5ef - */ 0, + /* 5f0 - */ 0, + /* 5f1 - */ 0, + /* 5f2 - */ 0, + /* 5f3 - */ 0, + /* 5f4 - */ 0, + /* 5f5 - */ 0, + /* 5f6 - */ 0, + /* 5f7 - */ 0, + /* 5f8 - */ 0, + /* 5f9 - */ 0, + /* 5fa - */ 0, + /* 5fb - */ 0, + /* 5fc - */ 0, + /* 5fd - */ 0, + /* 5fe - */ 0, + /* 5ff - */ 0, + /* 600 - */ 0, + /* 601 - */ 0, + /* 602 - */ 0, + /* 603 - */ 0, + /* 604 - */ 0, + /* 605 - */ 0, + /* 606 - */ 0, + /* 607 - */ 0, + /* 608 - */ 0, + /* 609 - */ 0, + /* 60a - */ 0, + /* 60b - */ 0, + /* 60c - */ 0, + /* 60d - */ 0, + /* 60e - */ 0, + /* 60f - */ 0, + /* 610 - */ 0, + /* 611 - */ 0, + /* 612 - */ 0, + /* 613 - */ 0, + /* 614 - */ 0, + /* 615 - */ 0, + /* 616 - */ 0, + /* 617 - */ 0, + /* 618 - */ 0, + /* 619 - */ 0, + /* 61a - */ 0, + /* 61b - */ 0, + /* 61c - */ 0, + /* 61d - */ 0, + /* 61e - */ 0, + /* 61f - */ 0, + /* 620 - */ 0, + /* 621 - */ 0, + /* 622 - */ 0, + /* 623 - */ 0, + /* 624 - */ 0, + /* 625 - */ 0, + /* 626 - */ 0, + /* 627 - */ 0, + /* 628 - */ 0, + /* 629 - */ 0, + /* 62a - _0F_0F_8A */ 0x235e, + /* 62b - */ 0, + /* 62c - */ 0, + /* 62d - */ 0, + /* 62e - _0F_0F_8E */ 0x235f, + /* 62f - */ 0, + /* 630 - _0F_0F_90 */ 0x2360, + /* 631 - */ 0, + /* 632 - */ 0, + /* 633 - */ 0, + /* 634 - _0F_0F_94 */ 0x2361, + /* 635 - */ 0, + /* 636 - _0F_0F_96 */ 0x2362, + /* 637 - _0F_0F_97 */ 0x2363, + /* 638 - */ 0, + /* 639 - */ 0, + /* 63a - _0F_0F_9A */ 0x2364, + /* 63b - */ 0, + /* 63c - */ 0, + /* 63d - */ 0, + /* 63e - _0F_0F_9E */ 0x2365, + /* 63f - */ 0, + /* 640 - _0F_0F_A0 */ 0x2366, + /* 641 - */ 0, + /* 642 - */ 0, + /* 643 - */ 0, + /* 644 - _0F_0F_A4 */ 0x2367, + /* 645 - */ 0, + /* 646 - _0F_0F_A6 */ 0x2368, + /* 647 - _0F_0F_A7 */ 0x2369, + /* 648 - */ 0, + /* 649 - */ 0, + /* 64a - _0F_0F_AA */ 0x236a, + /* 64b - */ 0, + /* 64c - */ 0, + /* 64d - */ 0, + /* 64e - _0F_0F_AE */ 0x236b, + /* 64f - */ 0, + /* 650 - _0F_0F_B0 */ 0x236c, + /* 651 - */ 0, + /* 652 - */ 0, + /* 653 - */ 0, + /* 654 - _0F_0F_B4 */ 0x236d, + /* 655 - */ 0, + /* 656 - _0F_0F_B6 */ 0x236e, + /* 657 - _0F_0F_B7 */ 0x236f, + /* 658 - */ 0, + /* 659 - */ 0, + /* 65a - */ 0, + /* 65b - _0F_0F_BB */ 0x2370, + /* 65c - */ 0, + /* 65d - */ 0, + /* 65e - */ 0, + /* 65f - _0F_0F_BF */ 0x2371, + /* 660 - */ 0, + /* 661 - */ 0, + /* 662 - */ 0, + /* 663 - */ 0, + /* 664 - */ 0, + /* 665 - */ 0, + /* 666 - */ 0, + /* 667 - */ 0, + /* 668 - */ 0, + /* 669 - */ 0, + /* 66a - */ 0, + /* 66b - */ 0, + /* 66c - */ 0, + /* 66d - */ 0, + /* 66e - */ 0, + /* 66f - */ 0, + /* 670 - */ 0, + /* 671 - */ 0, + /* 672 - */ 0, + /* 673 - */ 0, + /* 674 - */ 0, + /* 675 - */ 0, + /* 676 - */ 0, + /* 677 - */ 0, + /* 678 - */ 0, + /* 679 - */ 0, + /* 67a - */ 0, + /* 67b - */ 0, + /* 67c - */ 0, + /* 67d - */ 0, + /* 67e - */ 0, + /* 67f - */ 0, + /* 680 - */ 0, + /* 681 - */ 0, + /* 682 - */ 0, + /* 683 - */ 0, + /* 684 - */ 0, + /* 685 - */ 0, + /* 686 - */ 0, + /* 687 - */ 0, + /* 688 - */ 0, + /* 689 - */ 0, + /* 68a - */ 0, + /* 68b - */ 0, + /* 68c - */ 0, + /* 68d - */ 0, + /* 68e - */ 0, + /* 68f - */ 0, + /* 690 - */ 0, + /* 691 - */ 0, + /* 692 - */ 0, + /* 693 - */ 0, + /* 694 - */ 0, + /* 695 - */ 0, + /* 696 - */ 0, + /* 697 - */ 0, + /* 698 - */ 0, + /* 699 - */ 0, + /* 69a - */ 0, + /* 69b - */ 0, + /* 69c - */ 0, + /* 69d - */ 0, + /* 69e - */ 0, + /* 69f - */ 0, + /* 6a0 - _0F_10 */ 0x2372, + /* 6a1 - _66_0F_10 */ 0x2373, + /* 6a2 - _F3_0F_10 */ 0x2374, + /* 6a3 - _F2_0F_10 */ 0x2375, + /* 6a4 - _V_0F_10 */ 0x4009, + /* 6a5 - _V_66_0F_10 */ 0x400a, + /* 6a6 - _V_F3_0F_10 */ 0x400b, + /* 6a7 - _V_F2_0F_10 */ 0x400c, + /* 6a8 - */ 0, + /* 6a9 - */ 0, + /* 6aa - _VRR_F3_0F_10 */ 0x400d, + /* 6ab - _VRR_F2_0F_10 */ 0x400e, + /* 6ac - _0F_11 */ 0x2376, + /* 6ad - _66_0F_11 */ 0x2377, + /* 6ae - _F3_0F_11 */ 0x2378, + /* 6af - _F2_0F_11 */ 0x2379, + /* 6b0 - _V_0F_11 */ 0x400f, + /* 6b1 - _V_66_0F_11 */ 0x4010, + /* 6b2 - _V_F3_0F_11 */ 0x4011, + /* 6b3 - _V_F2_0F_11 */ 0x4012, + /* 6b4 - */ 0, + /* 6b5 - */ 0, + /* 6b6 - _VRR_F3_0F_11 */ 0x4013, + /* 6b7 - _VRR_F2_0F_11 */ 0x4014, + /* 6b8 - _0F_12 */ 0x4015, + /* 6b9 - _66_0F_12 */ 0x237a, + /* 6ba - _F3_0F_12 */ 0x237b, + /* 6bb - _F2_0F_12 */ 0x237c, + /* 6bc - _V_0F_12 */ 0x4016, + /* 6bd - _V_66_0F_12 */ 0x4017, + /* 6be - _V_F3_0F_12 */ 0x4018, + /* 6bf - _V_F2_0F_12 */ 0x4019, + /* 6c0 - */ 0, + /* 6c1 - */ 0, + /* 6c2 - */ 0, + /* 6c3 - */ 0, + /* 6c4 - _0F_13 */ 0x237d, + /* 6c5 - _66_0F_13 */ 0x237e, + /* 6c6 - */ 0, + /* 6c7 - */ 0, + /* 6c8 - _V_0F_13 */ 0x401a, + /* 6c9 - _V_66_0F_13 */ 0x401b, + /* 6ca - */ 0, + /* 6cb - */ 0, + /* 6cc - */ 0, + /* 6cd - */ 0, + /* 6ce - */ 0, + /* 6cf - */ 0, + /* 6d0 - _0F_14 */ 0x237f, + /* 6d1 - _66_0F_14 */ 0x2380, + /* 6d2 - */ 0, + /* 6d3 - */ 0, + /* 6d4 - _V_0F_14 */ 0x401c, + /* 6d5 - _V_66_0F_14 */ 0x401d, + /* 6d6 - */ 0, + /* 6d7 - */ 0, + /* 6d8 - */ 0, + /* 6d9 - */ 0, + /* 6da - */ 0, + /* 6db - */ 0, + /* 6dc - _0F_15 */ 0x2381, + /* 6dd - _66_0F_15 */ 0x2382, + /* 6de - */ 0, + /* 6df - */ 0, + /* 6e0 - _V_0F_15 */ 0x401e, + /* 6e1 - _V_66_0F_15 */ 0x401f, + /* 6e2 - */ 0, + /* 6e3 - */ 0, + /* 6e4 - */ 0, + /* 6e5 - */ 0, + /* 6e6 - */ 0, + /* 6e7 - */ 0, + /* 6e8 - _0F_16 */ 0x4020, + /* 6e9 - _66_0F_16 */ 0x2383, + /* 6ea - _F3_0F_16 */ 0x2384, + /* 6eb - */ 0, + /* 6ec - _V_0F_16 */ 0x4021, + /* 6ed - _V_66_0F_16 */ 0x4022, + /* 6ee - _V_F3_0F_16 */ 0x4023, + /* 6ef - */ 0, + /* 6f0 - */ 0, + /* 6f1 - */ 0, + /* 6f2 - */ 0, + /* 6f3 - */ 0, + /* 6f4 - _0F_17 */ 0x2385, + /* 6f5 - _66_0F_17 */ 0x2386, + /* 6f6 - */ 0, + /* 6f7 - */ 0, + /* 6f8 - _V_0F_17 */ 0x4024, + /* 6f9 - _V_66_0F_17 */ 0x4025, + /* 6fa - */ 0, + /* 6fb - */ 0, + /* 6fc - */ 0, + /* 6fd - */ 0, + /* 6fe - */ 0, + /* 6ff - */ 0, + /* 700 - _0F_18_00 */ 0x2387, + /* 701 - _0F_18_01 */ 0x2388, + /* 702 - _0F_18_02 */ 0x2389, + /* 703 - _0F_18_03 */ 0x238a, + /* 704 - */ 0, + /* 705 - */ 0, + /* 706 - */ 0, + /* 707 - */ 0, + /* 708 - _0F_28 */ 0x238b, + /* 709 - _66_0F_28 */ 0x238c, + /* 70a - */ 0, + /* 70b - */ 0, + /* 70c - _V_0F_28 */ 0x4026, + /* 70d - _V_66_0F_28 */ 0x4027, + /* 70e - */ 0, + /* 70f - */ 0, + /* 710 - */ 0, + /* 711 - */ 0, + /* 712 - */ 0, + /* 713 - */ 0, + /* 714 - _0F_29 */ 0x238d, + /* 715 - _66_0F_29 */ 0x238e, + /* 716 - */ 0, + /* 717 - */ 0, + /* 718 - _V_0F_29 */ 0x4028, + /* 719 - _V_66_0F_29 */ 0x4029, + /* 71a - */ 0, + /* 71b - */ 0, + /* 71c - */ 0, + /* 71d - */ 0, + /* 71e - */ 0, + /* 71f - */ 0, + /* 720 - _0F_2A */ 0x238f, + /* 721 - _66_0F_2A */ 0x2390, + /* 722 - _F3_0F_2A */ 0x2391, + /* 723 - _F2_0F_2A */ 0x2392, + /* 724 - */ 0, + /* 725 - */ 0, + /* 726 - _V_F3_0F_2A */ 0x402a, + /* 727 - _V_F2_0F_2A */ 0x402b, + /* 728 - */ 0, + /* 729 - */ 0, + /* 72a - */ 0, + /* 72b - */ 0, + /* 72c - _0F_2B */ 0x2393, + /* 72d - _66_0F_2B */ 0x2394, + /* 72e - _F3_0F_2B */ 0x2395, + /* 72f - _F2_0F_2B */ 0x2396, + /* 730 - _V_0F_2B */ 0x402c, + /* 731 - _V_66_0F_2B */ 0x402d, + /* 732 - */ 0, + /* 733 - */ 0, + /* 734 - */ 0, + /* 735 - */ 0, + /* 736 - */ 0, + /* 737 - */ 0, + /* 738 - _0F_2C */ 0x2397, + /* 739 - _66_0F_2C */ 0x2398, + /* 73a - _F3_0F_2C */ 0x2399, + /* 73b - _F2_0F_2C */ 0x239a, + /* 73c - */ 0, + /* 73d - */ 0, + /* 73e - _V_F3_0F_2C */ 0x402e, + /* 73f - _V_F2_0F_2C */ 0x402f, + /* 740 - */ 0, + /* 741 - */ 0, + /* 742 - */ 0, + /* 743 - */ 0, + /* 744 - _0F_2D */ 0x239b, + /* 745 - _66_0F_2D */ 0x239c, + /* 746 - _F3_0F_2D */ 0x239d, + /* 747 - _F2_0F_2D */ 0x239e, + /* 748 - */ 0, + /* 749 - */ 0, + /* 74a - _V_F3_0F_2D */ 0x4030, + /* 74b - _V_F2_0F_2D */ 0x4031, + /* 74c - */ 0, + /* 74d - */ 0, + /* 74e - */ 0, + /* 74f - */ 0, + /* 750 - _0F_2E */ 0x239f, + /* 751 - _66_0F_2E */ 0x23a0, + /* 752 - */ 0, + /* 753 - */ 0, + /* 754 - _V_0F_2E */ 0x4032, + /* 755 - _V_66_0F_2E */ 0x4033, + /* 756 - */ 0, + /* 757 - */ 0, + /* 758 - */ 0, + /* 759 - */ 0, + /* 75a - */ 0, + /* 75b - */ 0, + /* 75c - _0F_2F */ 0x23a1, + /* 75d - _66_0F_2F */ 0x23a2, + /* 75e - */ 0, + /* 75f - */ 0, + /* 760 - _V_0F_2F */ 0x4034, + /* 761 - _V_66_0F_2F */ 0x4035, + /* 762 - */ 0, + /* 763 - */ 0, + /* 764 - */ 0, + /* 765 - */ 0, + /* 766 - */ 0, + /* 767 - */ 0, + /* 768 - _0F_38_00 */ 0xcf78, + /* 769 - _0F_38_01 */ 0xcf84, + /* 76a - _0F_38_02 */ 0xcf90, + /* 76b - _0F_38_03 */ 0xcf9c, + /* 76c - _0F_38_04 */ 0xcfa8, + /* 76d - _0F_38_05 */ 0xcfb4, + /* 76e - _0F_38_06 */ 0xcfc0, + /* 76f - _0F_38_07 */ 0xcfcc, + /* 770 - _0F_38_08 */ 0xcfd8, + /* 771 - _0F_38_09 */ 0xcfe4, + /* 772 - _0F_38_0A */ 0xcff0, + /* 773 - _0F_38_0B */ 0xcffc, + /* 774 - _0F_38_0C */ 0xd008, + /* 775 - _0F_38_0D */ 0xd014, + /* 776 - _0F_38_0E */ 0xd020, + /* 777 - _0F_38_0F */ 0xd02c, + /* 778 - _0F_38_10 */ 0xd038, + /* 779 - */ 0, + /* 77a - */ 0, + /* 77b - */ 0, + /* 77c - _0F_38_14 */ 0xd044, + /* 77d - _0F_38_15 */ 0xd050, + /* 77e - */ 0, + /* 77f - _0F_38_17 */ 0xd05c, + /* 780 - _0F_38_18 */ 0xd068, + /* 781 - _0F_38_19 */ 0xd074, + /* 782 - _0F_38_1A */ 0xd080, + /* 783 - */ 0, + /* 784 - _0F_38_1C */ 0xd08c, + /* 785 - _0F_38_1D */ 0xd098, + /* 786 - _0F_38_1E */ 0xd0a4, + /* 787 - */ 0, + /* 788 - _0F_38_20 */ 0xd0b0, + /* 789 - _0F_38_21 */ 0xd0bc, + /* 78a - _0F_38_22 */ 0xd0c8, + /* 78b - _0F_38_23 */ 0xd0d4, + /* 78c - _0F_38_24 */ 0xd0e0, + /* 78d - _0F_38_25 */ 0xd0ec, + /* 78e - */ 0, + /* 78f - */ 0, + /* 790 - _0F_38_28 */ 0xd0f8, + /* 791 - _0F_38_29 */ 0xd104, + /* 792 - _0F_38_2A */ 0xd110, + /* 793 - _0F_38_2B */ 0xd11c, + /* 794 - _0F_38_2C */ 0xd128, + /* 795 - _0F_38_2D */ 0xd134, + /* 796 - _0F_38_2E */ 0xd140, + /* 797 - _0F_38_2F */ 0xd14c, + /* 798 - _0F_38_30 */ 0xd158, + /* 799 - _0F_38_31 */ 0xd164, + /* 79a - _0F_38_32 */ 0xd170, + /* 79b - _0F_38_33 */ 0xd17c, + /* 79c - _0F_38_34 */ 0xd188, + /* 79d - _0F_38_35 */ 0xd194, + /* 79e - */ 0, + /* 79f - _0F_38_37 */ 0xd1a0, + /* 7a0 - _0F_38_38 */ 0xd1ac, + /* 7a1 - _0F_38_39 */ 0xd1b8, + /* 7a2 - _0F_38_3A */ 0xd1c4, + /* 7a3 - _0F_38_3B */ 0xd1d0, + /* 7a4 - _0F_38_3C */ 0xd1dc, + /* 7a5 - _0F_38_3D */ 0xd1e8, + /* 7a6 - _0F_38_3E */ 0xd1f4, + /* 7a7 - _0F_38_3F */ 0xd200, + /* 7a8 - _0F_38_40 */ 0xd20c, + /* 7a9 - _0F_38_41 */ 0xd218, + /* 7aa - */ 0, + /* 7ab - */ 0, + /* 7ac - */ 0, + /* 7ad - */ 0, + /* 7ae - */ 0, + /* 7af - */ 0, + /* 7b0 - */ 0, + /* 7b1 - */ 0, + /* 7b2 - */ 0, + /* 7b3 - */ 0, + /* 7b4 - */ 0, + /* 7b5 - */ 0, + /* 7b6 - */ 0, + /* 7b7 - */ 0, + /* 7b8 - */ 0, + /* 7b9 - */ 0, + /* 7ba - */ 0, + /* 7bb - */ 0, + /* 7bc - */ 0, + /* 7bd - */ 0, + /* 7be - */ 0, + /* 7bf - */ 0, + /* 7c0 - */ 0, + /* 7c1 - */ 0, + /* 7c2 - */ 0, + /* 7c3 - */ 0, + /* 7c4 - */ 0, + /* 7c5 - */ 0, + /* 7c6 - */ 0, + /* 7c7 - */ 0, + /* 7c8 - */ 0, + /* 7c9 - */ 0, + /* 7ca - */ 0, + /* 7cb - */ 0, + /* 7cc - */ 0, + /* 7cd - */ 0, + /* 7ce - */ 0, + /* 7cf - */ 0, + /* 7d0 - */ 0, + /* 7d1 - */ 0, + /* 7d2 - */ 0, + /* 7d3 - */ 0, + /* 7d4 - */ 0, + /* 7d5 - */ 0, + /* 7d6 - */ 0, + /* 7d7 - */ 0, + /* 7d8 - */ 0, + /* 7d9 - */ 0, + /* 7da - */ 0, + /* 7db - */ 0, + /* 7dc - */ 0, + /* 7dd - */ 0, + /* 7de - */ 0, + /* 7df - */ 0, + /* 7e0 - */ 0, + /* 7e1 - */ 0, + /* 7e2 - */ 0, + /* 7e3 - */ 0, + /* 7e4 - */ 0, + /* 7e5 - */ 0, + /* 7e6 - */ 0, + /* 7e7 - */ 0, + /* 7e8 - _0F_38_80 */ 0xd224, + /* 7e9 - _0F_38_81 */ 0xd230, + /* 7ea - _0F_38_82 */ 0xd23c, + /* 7eb - */ 0, + /* 7ec - */ 0, + /* 7ed - */ 0, + /* 7ee - */ 0, + /* 7ef - */ 0, + /* 7f0 - */ 0, + /* 7f1 - */ 0, + /* 7f2 - */ 0, + /* 7f3 - */ 0, + /* 7f4 - */ 0, + /* 7f5 - */ 0, + /* 7f6 - */ 0, + /* 7f7 - */ 0, + /* 7f8 - */ 0, + /* 7f9 - */ 0, + /* 7fa - */ 0, + /* 7fb - */ 0, + /* 7fc - */ 0, + /* 7fd - */ 0, + /* 7fe - _0F_38_96 */ 0xd248, + /* 7ff - _0F_38_97 */ 0xd254, + /* 800 - _0F_38_98 */ 0xd260, + /* 801 - _0F_38_99 */ 0xd26c, + /* 802 - _0F_38_9A */ 0xd278, + /* 803 - _0F_38_9B */ 0xd284, + /* 804 - _0F_38_9C */ 0xd290, + /* 805 - _0F_38_9D */ 0xd29c, + /* 806 - _0F_38_9E */ 0xd2a8, + /* 807 - _0F_38_9F */ 0xd2b4, + /* 808 - */ 0, + /* 809 - */ 0, + /* 80a - */ 0, + /* 80b - */ 0, + /* 80c - */ 0, + /* 80d - */ 0, + /* 80e - _0F_38_A6 */ 0xd2c0, + /* 80f - _0F_38_A7 */ 0xd2cc, + /* 810 - _0F_38_A8 */ 0xd2d8, + /* 811 - _0F_38_A9 */ 0xd2e4, + /* 812 - _0F_38_AA */ 0xd2f0, + /* 813 - _0F_38_AB */ 0xd2fc, + /* 814 - _0F_38_AC */ 0xd308, + /* 815 - _0F_38_AD */ 0xd314, + /* 816 - _0F_38_AE */ 0xd320, + /* 817 - _0F_38_AF */ 0xd32c, + /* 818 - */ 0, + /* 819 - */ 0, + /* 81a - */ 0, + /* 81b - */ 0, + /* 81c - */ 0, + /* 81d - */ 0, + /* 81e - _0F_38_B6 */ 0xd338, + /* 81f - _0F_38_B7 */ 0xd344, + /* 820 - _0F_38_B8 */ 0xd350, + /* 821 - _0F_38_B9 */ 0xd35c, + /* 822 - _0F_38_BA */ 0xd368, + /* 823 - _0F_38_BB */ 0xd374, + /* 824 - _0F_38_BC */ 0xd380, + /* 825 - _0F_38_BD */ 0xd38c, + /* 826 - _0F_38_BE */ 0xd398, + /* 827 - _0F_38_BF */ 0xd3a4, + /* 828 - */ 0, + /* 829 - */ 0, + /* 82a - */ 0, + /* 82b - */ 0, + /* 82c - */ 0, + /* 82d - */ 0, + /* 82e - */ 0, + /* 82f - */ 0, + /* 830 - */ 0, + /* 831 - */ 0, + /* 832 - */ 0, + /* 833 - */ 0, + /* 834 - */ 0, + /* 835 - */ 0, + /* 836 - */ 0, + /* 837 - */ 0, + /* 838 - */ 0, + /* 839 - */ 0, + /* 83a - */ 0, + /* 83b - */ 0, + /* 83c - */ 0, + /* 83d - */ 0, + /* 83e - */ 0, + /* 83f - */ 0, + /* 840 - */ 0, + /* 841 - */ 0, + /* 842 - */ 0, + /* 843 - _0F_38_DB */ 0xd3b0, + /* 844 - _0F_38_DC */ 0xd3bc, + /* 845 - _0F_38_DD */ 0xd3c8, + /* 846 - _0F_38_DE */ 0xd3d4, + /* 847 - _0F_38_DF */ 0xd3e0, + /* 848 - */ 0, + /* 849 - */ 0, + /* 84a - */ 0, + /* 84b - */ 0, + /* 84c - */ 0, + /* 84d - */ 0, + /* 84e - */ 0, + /* 84f - */ 0, + /* 850 - */ 0, + /* 851 - */ 0, + /* 852 - */ 0, + /* 853 - */ 0, + /* 854 - */ 0, + /* 855 - */ 0, + /* 856 - */ 0, + /* 857 - */ 0, + /* 858 - _0F_38_F0 */ 0xd3ec, + /* 859 - _0F_38_F1 */ 0xd3f8, + /* 85a - */ 0, + /* 85b - */ 0, + /* 85c - */ 0, + /* 85d - */ 0, + /* 85e - */ 0, + /* 85f - */ 0, + /* 860 - */ 0, + /* 861 - */ 0, + /* 862 - */ 0, + /* 863 - */ 0, + /* 864 - */ 0, + /* 865 - */ 0, + /* 866 - */ 0, + /* 867 - */ 0, + /* 868 - */ 0, + /* 869 - */ 0, + /* 86a - */ 0, + /* 86b - */ 0, + /* 86c - _0F_3A_04 */ 0xd404, + /* 86d - _0F_3A_05 */ 0xd410, + /* 86e - _0F_3A_06 */ 0xd41c, + /* 86f - */ 0, + /* 870 - _0F_3A_08 */ 0xd428, + /* 871 - _0F_3A_09 */ 0xd434, + /* 872 - _0F_3A_0A */ 0xd440, + /* 873 - _0F_3A_0B */ 0xd44c, + /* 874 - _0F_3A_0C */ 0xd458, + /* 875 - _0F_3A_0D */ 0xd464, + /* 876 - _0F_3A_0E */ 0xd470, + /* 877 - _0F_3A_0F */ 0xd47c, + /* 878 - */ 0, + /* 879 - */ 0, + /* 87a - */ 0, + /* 87b - */ 0, + /* 87c - _0F_3A_14 */ 0xd488, + /* 87d - _0F_3A_15 */ 0xd494, + /* 87e - _0F_3A_16 */ 0xd4a0, + /* 87f - _0F_3A_17 */ 0xd4ac, + /* 880 - _0F_3A_18 */ 0xd4b8, + /* 881 - _0F_3A_19 */ 0xd4c4, + /* 882 - */ 0, + /* 883 - */ 0, + /* 884 - */ 0, + /* 885 - */ 0, + /* 886 - */ 0, + /* 887 - */ 0, + /* 888 - _0F_3A_20 */ 0xd4d0, + /* 889 - _0F_3A_21 */ 0xd4dc, + /* 88a - _0F_3A_22 */ 0xd4e8, + /* 88b - */ 0, + /* 88c - */ 0, + /* 88d - */ 0, + /* 88e - */ 0, + /* 88f - */ 0, + /* 890 - */ 0, + /* 891 - */ 0, + /* 892 - */ 0, + /* 893 - */ 0, + /* 894 - */ 0, + /* 895 - */ 0, + /* 896 - */ 0, + /* 897 - */ 0, + /* 898 - */ 0, + /* 899 - */ 0, + /* 89a - */ 0, + /* 89b - */ 0, + /* 89c - */ 0, + /* 89d - */ 0, + /* 89e - */ 0, + /* 89f - */ 0, + /* 8a0 - */ 0, + /* 8a1 - */ 0, + /* 8a2 - */ 0, + /* 8a3 - */ 0, + /* 8a4 - */ 0, + /* 8a5 - */ 0, + /* 8a6 - */ 0, + /* 8a7 - */ 0, + /* 8a8 - _0F_3A_40 */ 0xd4f4, + /* 8a9 - _0F_3A_41 */ 0xd500, + /* 8aa - _0F_3A_42 */ 0xd50c, + /* 8ab - */ 0, + /* 8ac - _0F_3A_44 */ 0xd518, + /* 8ad - */ 0, + /* 8ae - */ 0, + /* 8af - */ 0, + /* 8b0 - */ 0, + /* 8b1 - */ 0, + /* 8b2 - _0F_3A_4A */ 0xd524, + /* 8b3 - _0F_3A_4B */ 0xd530, + /* 8b4 - _0F_3A_4C */ 0xd53c, + /* 8b5 - */ 0, + /* 8b6 - */ 0, + /* 8b7 - */ 0, + /* 8b8 - */ 0, + /* 8b9 - */ 0, + /* 8ba - */ 0, + /* 8bb - */ 0, + /* 8bc - */ 0, + /* 8bd - */ 0, + /* 8be - */ 0, + /* 8bf - */ 0, + /* 8c0 - */ 0, + /* 8c1 - */ 0, + /* 8c2 - */ 0, + /* 8c3 - */ 0, + /* 8c4 - */ 0, + /* 8c5 - */ 0, + /* 8c6 - */ 0, + /* 8c7 - */ 0, + /* 8c8 - _0F_3A_60 */ 0xd548, + /* 8c9 - _0F_3A_61 */ 0xd554, + /* 8ca - _0F_3A_62 */ 0xd560, + /* 8cb - _0F_3A_63 */ 0xd56c, + /* 8cc - */ 0, + /* 8cd - */ 0, + /* 8ce - */ 0, + /* 8cf - */ 0, + /* 8d0 - */ 0, + /* 8d1 - */ 0, + /* 8d2 - */ 0, + /* 8d3 - */ 0, + /* 8d4 - */ 0, + /* 8d5 - */ 0, + /* 8d6 - */ 0, + /* 8d7 - */ 0, + /* 8d8 - */ 0, + /* 8d9 - */ 0, + /* 8da - */ 0, + /* 8db - */ 0, + /* 8dc - */ 0, + /* 8dd - */ 0, + /* 8de - */ 0, + /* 8df - */ 0, + /* 8e0 - */ 0, + /* 8e1 - */ 0, + /* 8e2 - */ 0, + /* 8e3 - */ 0, + /* 8e4 - */ 0, + /* 8e5 - */ 0, + /* 8e6 - */ 0, + /* 8e7 - */ 0, + /* 8e8 - */ 0, + /* 8e9 - */ 0, + /* 8ea - */ 0, + /* 8eb - */ 0, + /* 8ec - */ 0, + /* 8ed - */ 0, + /* 8ee - */ 0, + /* 8ef - */ 0, + /* 8f0 - */ 0, + /* 8f1 - */ 0, + /* 8f2 - */ 0, + /* 8f3 - */ 0, + /* 8f4 - */ 0, + /* 8f5 - */ 0, + /* 8f6 - */ 0, + /* 8f7 - */ 0, + /* 8f8 - */ 0, + /* 8f9 - */ 0, + /* 8fa - */ 0, + /* 8fb - */ 0, + /* 8fc - */ 0, + /* 8fd - */ 0, + /* 8fe - */ 0, + /* 8ff - */ 0, + /* 900 - */ 0, + /* 901 - */ 0, + /* 902 - */ 0, + /* 903 - */ 0, + /* 904 - */ 0, + /* 905 - */ 0, + /* 906 - */ 0, + /* 907 - */ 0, + /* 908 - */ 0, + /* 909 - */ 0, + /* 90a - */ 0, + /* 90b - */ 0, + /* 90c - */ 0, + /* 90d - */ 0, + /* 90e - */ 0, + /* 90f - */ 0, + /* 910 - */ 0, + /* 911 - */ 0, + /* 912 - */ 0, + /* 913 - */ 0, + /* 914 - */ 0, + /* 915 - */ 0, + /* 916 - */ 0, + /* 917 - */ 0, + /* 918 - */ 0, + /* 919 - */ 0, + /* 91a - */ 0, + /* 91b - */ 0, + /* 91c - */ 0, + /* 91d - */ 0, + /* 91e - */ 0, + /* 91f - */ 0, + /* 920 - */ 0, + /* 921 - */ 0, + /* 922 - */ 0, + /* 923 - */ 0, + /* 924 - */ 0, + /* 925 - */ 0, + /* 926 - */ 0, + /* 927 - */ 0, + /* 928 - */ 0, + /* 929 - */ 0, + /* 92a - */ 0, + /* 92b - */ 0, + /* 92c - */ 0, + /* 92d - */ 0, + /* 92e - */ 0, + /* 92f - */ 0, + /* 930 - */ 0, + /* 931 - */ 0, + /* 932 - */ 0, + /* 933 - */ 0, + /* 934 - */ 0, + /* 935 - */ 0, + /* 936 - */ 0, + /* 937 - */ 0, + /* 938 - */ 0, + /* 939 - */ 0, + /* 93a - */ 0, + /* 93b - */ 0, + /* 93c - */ 0, + /* 93d - */ 0, + /* 93e - */ 0, + /* 93f - */ 0, + /* 940 - */ 0, + /* 941 - */ 0, + /* 942 - */ 0, + /* 943 - */ 0, + /* 944 - */ 0, + /* 945 - */ 0, + /* 946 - */ 0, + /* 947 - _0F_3A_DF */ 0xd578, + /* 948 - */ 0, + /* 949 - */ 0, + /* 94a - */ 0, + /* 94b - */ 0, + /* 94c - */ 0, + /* 94d - */ 0, + /* 94e - */ 0, + /* 94f - */ 0, + /* 950 - */ 0, + /* 951 - */ 0, + /* 952 - */ 0, + /* 953 - */ 0, + /* 954 - */ 0, + /* 955 - */ 0, + /* 956 - */ 0, + /* 957 - */ 0, + /* 958 - */ 0, + /* 959 - */ 0, + /* 95a - */ 0, + /* 95b - */ 0, + /* 95c - */ 0, + /* 95d - */ 0, + /* 95e - */ 0, + /* 95f - */ 0, + /* 960 - */ 0, + /* 961 - */ 0, + /* 962 - */ 0, + /* 963 - */ 0, + /* 964 - */ 0, + /* 965 - */ 0, + /* 966 - */ 0, + /* 967 - */ 0, + /* 968 - _0F_50 */ 0x23a3, + /* 969 - _66_0F_50 */ 0x23a4, + /* 96a - */ 0, + /* 96b - */ 0, + /* 96c - _V_0F_50 */ 0x4036, + /* 96d - _V_66_0F_50 */ 0x4037, + /* 96e - */ 0, + /* 96f - */ 0, + /* 970 - */ 0, + /* 971 - */ 0, + /* 972 - */ 0, + /* 973 - */ 0, + /* 974 - _0F_51 */ 0x23a5, + /* 975 - _66_0F_51 */ 0x23a6, + /* 976 - _F3_0F_51 */ 0x23a7, + /* 977 - _F2_0F_51 */ 0x23a8, + /* 978 - _V_0F_51 */ 0x4038, + /* 979 - _V_66_0F_51 */ 0x4039, + /* 97a - _V_F3_0F_51 */ 0x403a, + /* 97b - _V_F2_0F_51 */ 0x403b, + /* 97c - */ 0, + /* 97d - */ 0, + /* 97e - */ 0, + /* 97f - */ 0, + /* 980 - _0F_52 */ 0x23a9, + /* 981 - */ 0, + /* 982 - _F3_0F_52 */ 0x23aa, + /* 983 - */ 0, + /* 984 - _V_0F_52 */ 0x403c, + /* 985 - */ 0, + /* 986 - _V_F3_0F_52 */ 0x403d, + /* 987 - */ 0, + /* 988 - */ 0, + /* 989 - */ 0, + /* 98a - */ 0, + /* 98b - */ 0, + /* 98c - _0F_53 */ 0x23ab, + /* 98d - */ 0, + /* 98e - _F3_0F_53 */ 0x23ac, + /* 98f - */ 0, + /* 990 - _V_0F_53 */ 0x403e, + /* 991 - */ 0, + /* 992 - _V_F3_0F_53 */ 0x403f, + /* 993 - */ 0, + /* 994 - */ 0, + /* 995 - */ 0, + /* 996 - */ 0, + /* 997 - */ 0, + /* 998 - _0F_54 */ 0x23ad, + /* 999 - _66_0F_54 */ 0x23ae, + /* 99a - */ 0, + /* 99b - */ 0, + /* 99c - _V_0F_54 */ 0x4040, + /* 99d - _V_66_0F_54 */ 0x4041, + /* 99e - */ 0, + /* 99f - */ 0, + /* 9a0 - */ 0, + /* 9a1 - */ 0, + /* 9a2 - */ 0, + /* 9a3 - */ 0, + /* 9a4 - _0F_55 */ 0x23af, + /* 9a5 - _66_0F_55 */ 0x23b0, + /* 9a6 - */ 0, + /* 9a7 - */ 0, + /* 9a8 - _V_0F_55 */ 0x4042, + /* 9a9 - _V_66_0F_55 */ 0x4043, + /* 9aa - */ 0, + /* 9ab - */ 0, + /* 9ac - */ 0, + /* 9ad - */ 0, + /* 9ae - */ 0, + /* 9af - */ 0, + /* 9b0 - _0F_56 */ 0x23b1, + /* 9b1 - _66_0F_56 */ 0x23b2, + /* 9b2 - */ 0, + /* 9b3 - */ 0, + /* 9b4 - _V_0F_56 */ 0x4044, + /* 9b5 - _V_66_0F_56 */ 0x4045, + /* 9b6 - */ 0, + /* 9b7 - */ 0, + /* 9b8 - */ 0, + /* 9b9 - */ 0, + /* 9ba - */ 0, + /* 9bb - */ 0, + /* 9bc - _0F_57 */ 0x23b3, + /* 9bd - _66_0F_57 */ 0x23b4, + /* 9be - */ 0, + /* 9bf - */ 0, + /* 9c0 - _V_0F_57 */ 0x4046, + /* 9c1 - _V_66_0F_57 */ 0x4047, + /* 9c2 - */ 0, + /* 9c3 - */ 0, + /* 9c4 - */ 0, + /* 9c5 - */ 0, + /* 9c6 - */ 0, + /* 9c7 - */ 0, + /* 9c8 - _0F_58 */ 0x23b5, + /* 9c9 - _66_0F_58 */ 0x23b6, + /* 9ca - _F3_0F_58 */ 0x23b7, + /* 9cb - _F2_0F_58 */ 0x23b8, + /* 9cc - _V_0F_58 */ 0x4048, + /* 9cd - _V_66_0F_58 */ 0x4049, + /* 9ce - _V_F3_0F_58 */ 0x404a, + /* 9cf - _V_F2_0F_58 */ 0x404b, + /* 9d0 - */ 0, + /* 9d1 - */ 0, + /* 9d2 - */ 0, + /* 9d3 - */ 0, + /* 9d4 - _0F_59 */ 0x23b9, + /* 9d5 - _66_0F_59 */ 0x23ba, + /* 9d6 - _F3_0F_59 */ 0x23bb, + /* 9d7 - _F2_0F_59 */ 0x23bc, + /* 9d8 - _V_0F_59 */ 0x404c, + /* 9d9 - _V_66_0F_59 */ 0x404d, + /* 9da - _V_F3_0F_59 */ 0x404e, + /* 9db - _V_F2_0F_59 */ 0x404f, + /* 9dc - */ 0, + /* 9dd - */ 0, + /* 9de - */ 0, + /* 9df - */ 0, + /* 9e0 - _0F_5A */ 0x23bd, + /* 9e1 - _66_0F_5A */ 0x23be, + /* 9e2 - _F3_0F_5A */ 0x23bf, + /* 9e3 - _F2_0F_5A */ 0x23c0, + /* 9e4 - _V_0F_5A */ 0x4050, + /* 9e5 - _V_66_0F_5A */ 0x4051, + /* 9e6 - _V_F3_0F_5A */ 0x4052, + /* 9e7 - _V_F2_0F_5A */ 0x4053, + /* 9e8 - */ 0, + /* 9e9 - */ 0, + /* 9ea - */ 0, + /* 9eb - */ 0, + /* 9ec - _0F_5B */ 0x23c1, + /* 9ed - _66_0F_5B */ 0x23c2, + /* 9ee - _F3_0F_5B */ 0x23c3, + /* 9ef - */ 0, + /* 9f0 - _V_0F_5B */ 0x4054, + /* 9f1 - _V_66_0F_5B */ 0x4055, + /* 9f2 - _V_F3_0F_5B */ 0x4056, + /* 9f3 - */ 0, + /* 9f4 - */ 0, + /* 9f5 - */ 0, + /* 9f6 - */ 0, + /* 9f7 - */ 0, + /* 9f8 - _0F_5C */ 0x23c4, + /* 9f9 - _66_0F_5C */ 0x23c5, + /* 9fa - _F3_0F_5C */ 0x23c6, + /* 9fb - _F2_0F_5C */ 0x23c7, + /* 9fc - _V_0F_5C */ 0x4057, + /* 9fd - _V_66_0F_5C */ 0x4058, + /* 9fe - _V_F3_0F_5C */ 0x4059, + /* 9ff - _V_F2_0F_5C */ 0x405a, + /* a00 - */ 0, + /* a01 - */ 0, + /* a02 - */ 0, + /* a03 - */ 0, + /* a04 - _0F_5D */ 0x23c8, + /* a05 - _66_0F_5D */ 0x23c9, + /* a06 - _F3_0F_5D */ 0x23ca, + /* a07 - _F2_0F_5D */ 0x23cb, + /* a08 - _V_0F_5D */ 0x405b, + /* a09 - _V_66_0F_5D */ 0x405c, + /* a0a - _V_F3_0F_5D */ 0x405d, + /* a0b - _V_F2_0F_5D */ 0x405e, + /* a0c - */ 0, + /* a0d - */ 0, + /* a0e - */ 0, + /* a0f - */ 0, + /* a10 - _0F_5E */ 0x23cc, + /* a11 - _66_0F_5E */ 0x23cd, + /* a12 - _F3_0F_5E */ 0x23ce, + /* a13 - _F2_0F_5E */ 0x23cf, + /* a14 - _V_0F_5E */ 0x405f, + /* a15 - _V_66_0F_5E */ 0x4060, + /* a16 - _V_F3_0F_5E */ 0x4061, + /* a17 - _V_F2_0F_5E */ 0x4062, + /* a18 - */ 0, + /* a19 - */ 0, + /* a1a - */ 0, + /* a1b - */ 0, + /* a1c - _0F_5F */ 0x23d0, + /* a1d - _66_0F_5F */ 0x23d1, + /* a1e - _F3_0F_5F */ 0x23d2, + /* a1f - _F2_0F_5F */ 0x23d3, + /* a20 - _V_0F_5F */ 0x4063, + /* a21 - _V_66_0F_5F */ 0x4064, + /* a22 - _V_F3_0F_5F */ 0x4065, + /* a23 - _V_F2_0F_5F */ 0x4066, + /* a24 - */ 0, + /* a25 - */ 0, + /* a26 - */ 0, + /* a27 - */ 0, + /* a28 - _0F_60 */ 0x23d4, + /* a29 - _66_0F_60 */ 0x23d5, + /* a2a - */ 0, + /* a2b - */ 0, + /* a2c - */ 0, + /* a2d - _V_66_0F_60 */ 0x4067, + /* a2e - */ 0, + /* a2f - */ 0, + /* a30 - */ 0, + /* a31 - */ 0, + /* a32 - */ 0, + /* a33 - */ 0, + /* a34 - _0F_61 */ 0x23d6, + /* a35 - _66_0F_61 */ 0x23d7, + /* a36 - */ 0, + /* a37 - */ 0, + /* a38 - */ 0, + /* a39 - _V_66_0F_61 */ 0x4068, + /* a3a - */ 0, + /* a3b - */ 0, + /* a3c - */ 0, + /* a3d - */ 0, + /* a3e - */ 0, + /* a3f - */ 0, + /* a40 - _0F_62 */ 0x23d8, + /* a41 - _66_0F_62 */ 0x23d9, + /* a42 - */ 0, + /* a43 - */ 0, + /* a44 - */ 0, + /* a45 - _V_66_0F_62 */ 0x4069, + /* a46 - */ 0, + /* a47 - */ 0, + /* a48 - */ 0, + /* a49 - */ 0, + /* a4a - */ 0, + /* a4b - */ 0, + /* a4c - _0F_63 */ 0x23da, + /* a4d - _66_0F_63 */ 0x23db, + /* a4e - */ 0, + /* a4f - */ 0, + /* a50 - */ 0, + /* a51 - _V_66_0F_63 */ 0x406a, + /* a52 - */ 0, + /* a53 - */ 0, + /* a54 - */ 0, + /* a55 - */ 0, + /* a56 - */ 0, + /* a57 - */ 0, + /* a58 - _0F_64 */ 0x23dc, + /* a59 - _66_0F_64 */ 0x23dd, + /* a5a - */ 0, + /* a5b - */ 0, + /* a5c - */ 0, + /* a5d - _V_66_0F_64 */ 0x406b, + /* a5e - */ 0, + /* a5f - */ 0, + /* a60 - */ 0, + /* a61 - */ 0, + /* a62 - */ 0, + /* a63 - */ 0, + /* a64 - _0F_65 */ 0x23de, + /* a65 - _66_0F_65 */ 0x23df, + /* a66 - */ 0, + /* a67 - */ 0, + /* a68 - */ 0, + /* a69 - _V_66_0F_65 */ 0x406c, + /* a6a - */ 0, + /* a6b - */ 0, + /* a6c - */ 0, + /* a6d - */ 0, + /* a6e - */ 0, + /* a6f - */ 0, + /* a70 - _0F_66 */ 0x23e0, + /* a71 - _66_0F_66 */ 0x23e1, + /* a72 - */ 0, + /* a73 - */ 0, + /* a74 - */ 0, + /* a75 - _V_66_0F_66 */ 0x406d, + /* a76 - */ 0, + /* a77 - */ 0, + /* a78 - */ 0, + /* a79 - */ 0, + /* a7a - */ 0, + /* a7b - */ 0, + /* a7c - _0F_67 */ 0x23e2, + /* a7d - _66_0F_67 */ 0x23e3, + /* a7e - */ 0, + /* a7f - */ 0, + /* a80 - */ 0, + /* a81 - _V_66_0F_67 */ 0x406e, + /* a82 - */ 0, + /* a83 - */ 0, + /* a84 - */ 0, + /* a85 - */ 0, + /* a86 - */ 0, + /* a87 - */ 0, + /* a88 - _0F_68 */ 0x23e4, + /* a89 - _66_0F_68 */ 0x23e5, + /* a8a - */ 0, + /* a8b - */ 0, + /* a8c - */ 0, + /* a8d - _V_66_0F_68 */ 0x406f, + /* a8e - */ 0, + /* a8f - */ 0, + /* a90 - */ 0, + /* a91 - */ 0, + /* a92 - */ 0, + /* a93 - */ 0, + /* a94 - _0F_69 */ 0x23e6, + /* a95 - _66_0F_69 */ 0x23e7, + /* a96 - */ 0, + /* a97 - */ 0, + /* a98 - */ 0, + /* a99 - _V_66_0F_69 */ 0x4070, + /* a9a - */ 0, + /* a9b - */ 0, + /* a9c - */ 0, + /* a9d - */ 0, + /* a9e - */ 0, + /* a9f - */ 0, + /* aa0 - _0F_6A */ 0x23e8, + /* aa1 - _66_0F_6A */ 0x23e9, + /* aa2 - */ 0, + /* aa3 - */ 0, + /* aa4 - */ 0, + /* aa5 - _V_66_0F_6A */ 0x4071, + /* aa6 - */ 0, + /* aa7 - */ 0, + /* aa8 - */ 0, + /* aa9 - */ 0, + /* aaa - */ 0, + /* aab - */ 0, + /* aac - _0F_6B */ 0x23ea, + /* aad - _66_0F_6B */ 0x23eb, + /* aae - */ 0, + /* aaf - */ 0, + /* ab0 - */ 0, + /* ab1 - _V_66_0F_6B */ 0x4072, + /* ab2 - */ 0, + /* ab3 - */ 0, + /* ab4 - */ 0, + /* ab5 - */ 0, + /* ab6 - */ 0, + /* ab7 - */ 0, + /* ab8 - */ 0, + /* ab9 - _66_0F_6C */ 0x23ec, + /* aba - */ 0, + /* abb - */ 0, + /* abc - */ 0, + /* abd - _V_66_0F_6C */ 0x4073, + /* abe - */ 0, + /* abf - */ 0, + /* ac0 - */ 0, + /* ac1 - */ 0, + /* ac2 - */ 0, + /* ac3 - */ 0, + /* ac4 - */ 0, + /* ac5 - _66_0F_6D */ 0x23ed, + /* ac6 - */ 0, + /* ac7 - */ 0, + /* ac8 - */ 0, + /* ac9 - _V_66_0F_6D */ 0x4074, + /* aca - */ 0, + /* acb - */ 0, + /* acc - */ 0, + /* acd - */ 0, + /* ace - */ 0, + /* acf - */ 0, + /* ad0 - _0F_6E */ 0x4075, + /* ad1 - _66_0F_6E */ 0x4076, + /* ad2 - */ 0, + /* ad3 - */ 0, + /* ad4 - */ 0, + /* ad5 - _V_66_0F_6E */ 0x4077, + /* ad6 - */ 0, + /* ad7 - */ 0, + /* ad8 - */ 0, + /* ad9 - */ 0, + /* ada - */ 0, + /* adb - */ 0, + /* adc - _0F_6F */ 0x23ee, + /* add - _66_0F_6F */ 0x23ef, + /* ade - _F3_0F_6F */ 0x23f0, + /* adf - */ 0, + /* ae0 - */ 0, + /* ae1 - _V_66_0F_6F */ 0x4078, + /* ae2 - _V_F3_0F_6F */ 0x4079, + /* ae3 - */ 0, + /* ae4 - */ 0, + /* ae5 - */ 0, + /* ae6 - */ 0, + /* ae7 - */ 0, + /* ae8 - _0F_70 */ 0x407a, + /* ae9 - _66_0F_70 */ 0x407b, + /* aea - _F3_0F_70 */ 0x407c, + /* aeb - _F2_0F_70 */ 0x407d, + /* aec - */ 0, + /* aed - _V_66_0F_70 */ 0x407e, + /* aee - _V_F3_0F_70 */ 0x407f, + /* aef - _V_F2_0F_70 */ 0x4080, + /* af0 - */ 0, + /* af1 - */ 0, + /* af2 - */ 0, + /* af3 - */ 0, + /* af4 - */ 0, + /* af5 - */ 0, + /* af6 - _0F_71_02 */ 0xd584, + /* af7 - */ 0, + /* af8 - _0F_71_04 */ 0xd590, + /* af9 - */ 0, + /* afa - _0F_71_06 */ 0xd59c, + /* afb - */ 0, + /* afc - */ 0, + /* afd - */ 0, + /* afe - _0F_72_02 */ 0xd5a8, + /* aff - */ 0, + /* b00 - _0F_72_04 */ 0xd5b4, + /* b01 - */ 0, + /* b02 - _0F_72_06 */ 0xd5c0, + /* b03 - */ 0, + /* b04 - */ 0, + /* b05 - */ 0, + /* b06 - _0F_73_02 */ 0xd5cc, + /* b07 - _0F_73_03 */ 0xd5d8, + /* b08 - */ 0, + /* b09 - */ 0, + /* b0a - _0F_73_06 */ 0xd5e4, + /* b0b - _0F_73_07 */ 0xd5f0, + /* b0c - _0F_74 */ 0x23f1, + /* b0d - _66_0F_74 */ 0x23f2, + /* b0e - */ 0, + /* b0f - */ 0, + /* b10 - */ 0, + /* b11 - _V_66_0F_74 */ 0x4081, + /* b12 - */ 0, + /* b13 - */ 0, + /* b14 - */ 0, + /* b15 - */ 0, + /* b16 - */ 0, + /* b17 - */ 0, + /* b18 - _0F_75 */ 0x23f3, + /* b19 - _66_0F_75 */ 0x23f4, + /* b1a - */ 0, + /* b1b - */ 0, + /* b1c - */ 0, + /* b1d - _V_66_0F_75 */ 0x4082, + /* b1e - */ 0, + /* b1f - */ 0, + /* b20 - */ 0, + /* b21 - */ 0, + /* b22 - */ 0, + /* b23 - */ 0, + /* b24 - _0F_76 */ 0x23f5, + /* b25 - _66_0F_76 */ 0x23f6, + /* b26 - */ 0, + /* b27 - */ 0, + /* b28 - */ 0, + /* b29 - _V_66_0F_76 */ 0x4083, + /* b2a - */ 0, + /* b2b - */ 0, + /* b2c - */ 0, + /* b2d - */ 0, + /* b2e - */ 0, + /* b2f - */ 0, + /* b30 - _0F_77 */ 0x23f7, + /* b31 - */ 0, + /* b32 - */ 0, + /* b33 - */ 0, + /* b34 - _V_0F_77 */ 0x4084, + /* b35 - */ 0, + /* b36 - */ 0, + /* b37 - */ 0, + /* b38 - */ 0, + /* b39 - */ 0, + /* b3a - */ 0, + /* b3b - */ 0, + /* b3c - _0F_78 */ 0x23f8, + /* b3d - _66_0F_78 */ 0x4085, + /* b3e - */ 0, + /* b3f - _F2_0F_78 */ 0x4086, + /* b40 - */ 0, + /* b41 - */ 0, + /* b42 - */ 0, + /* b43 - */ 0, + /* b44 - */ 0, + /* b45 - */ 0, + /* b46 - */ 0, + /* b47 - */ 0, + /* b48 - _0F_79 */ 0x23f9, + /* b49 - _66_0F_79 */ 0x23fa, + /* b4a - */ 0, + /* b4b - _F2_0F_79 */ 0x23fb, + /* b4c - */ 0, + /* b4d - */ 0, + /* b4e - */ 0, + /* b4f - */ 0, + /* b50 - */ 0, + /* b51 - */ 0, + /* b52 - */ 0, + /* b53 - */ 0, + /* b54 - */ 0, + /* b55 - */ 0, + /* b56 - */ 0, + /* b57 - */ 0, + /* b58 - */ 0, + /* b59 - */ 0, + /* b5a - */ 0, + /* b5b - */ 0, + /* b5c - */ 0, + /* b5d - */ 0, + /* b5e - */ 0, + /* b5f - */ 0, + /* b60 - */ 0, + /* b61 - */ 0, + /* b62 - */ 0, + /* b63 - */ 0, + /* b64 - */ 0, + /* b65 - */ 0, + /* b66 - */ 0, + /* b67 - */ 0, + /* b68 - */ 0, + /* b69 - */ 0, + /* b6a - */ 0, + /* b6b - */ 0, + /* b6c - */ 0, + /* b6d - */ 0, + /* b6e - */ 0, + /* b6f - */ 0, + /* b70 - */ 0, + /* b71 - */ 0, + /* b72 - */ 0, + /* b73 - */ 0, + /* b74 - */ 0, + /* b75 - */ 0, + /* b76 - */ 0, + /* b77 - */ 0, + /* b78 - */ 0, + /* b79 - */ 0, + /* b7a - */ 0, + /* b7b - */ 0, + /* b7c - */ 0, + /* b7d - */ 0, + /* b7e - */ 0, + /* b7f - */ 0, + /* b80 - */ 0, + /* b81 - */ 0, + /* b82 - */ 0, + /* b83 - */ 0, + /* b84 - _0F_7A_30 */ 0x23fc, + /* b85 - _0F_7A_31 */ 0x23fd, + /* b86 - */ 0, + /* b87 - */ 0, + /* b88 - */ 0, + /* b89 - */ 0, + /* b8a - */ 0, + /* b8b - */ 0, + /* b8c - */ 0, + /* b8d - */ 0, + /* b8e - */ 0, + /* b8f - */ 0, + /* b90 - */ 0, + /* b91 - */ 0, + /* b92 - */ 0, + /* b93 - */ 0, + /* b94 - */ 0, + /* b95 - */ 0, + /* b96 - */ 0, + /* b97 - */ 0, + /* b98 - */ 0, + /* b99 - */ 0, + /* b9a - */ 0, + /* b9b - */ 0, + /* b9c - */ 0, + /* b9d - */ 0, + /* b9e - */ 0, + /* b9f - */ 0, + /* ba0 - */ 0, + /* ba1 - */ 0, + /* ba2 - */ 0, + /* ba3 - */ 0, + /* ba4 - */ 0, + /* ba5 - */ 0, + /* ba6 - */ 0, + /* ba7 - */ 0, + /* ba8 - */ 0, + /* ba9 - */ 0, + /* baa - */ 0, + /* bab - */ 0, + /* bac - */ 0, + /* bad - */ 0, + /* bae - */ 0, + /* baf - */ 0, + /* bb0 - */ 0, + /* bb1 - */ 0, + /* bb2 - */ 0, + /* bb3 - */ 0, + /* bb4 - */ 0, + /* bb5 - */ 0, + /* bb6 - */ 0, + /* bb7 - */ 0, + /* bb8 - */ 0, + /* bb9 - */ 0, + /* bba - */ 0, + /* bbb - */ 0, + /* bbc - */ 0, + /* bbd - */ 0, + /* bbe - */ 0, + /* bbf - */ 0, + /* bc0 - */ 0, + /* bc1 - */ 0, + /* bc2 - */ 0, + /* bc3 - */ 0, + /* bc4 - */ 0, + /* bc5 - */ 0, + /* bc6 - */ 0, + /* bc7 - */ 0, + /* bc8 - */ 0, + /* bc9 - */ 0, + /* bca - */ 0, + /* bcb - */ 0, + /* bcc - */ 0, + /* bcd - */ 0, + /* bce - */ 0, + /* bcf - */ 0, + /* bd0 - */ 0, + /* bd1 - */ 0, + /* bd2 - */ 0, + /* bd3 - */ 0, + /* bd4 - */ 0, + /* bd5 - */ 0, + /* bd6 - */ 0, + /* bd7 - */ 0, + /* bd8 - */ 0, + /* bd9 - */ 0, + /* bda - */ 0, + /* bdb - */ 0, + /* bdc - */ 0, + /* bdd - */ 0, + /* bde - */ 0, + /* bdf - */ 0, + /* be0 - */ 0, + /* be1 - */ 0, + /* be2 - */ 0, + /* be3 - */ 0, + /* be4 - */ 0, + /* be5 - */ 0, + /* be6 - */ 0, + /* be7 - */ 0, + /* be8 - */ 0, + /* be9 - */ 0, + /* bea - */ 0, + /* beb - */ 0, + /* bec - */ 0, + /* bed - */ 0, + /* bee - */ 0, + /* bef - */ 0, + /* bf0 - */ 0, + /* bf1 - */ 0, + /* bf2 - */ 0, + /* bf3 - */ 0, + /* bf4 - */ 0, + /* bf5 - */ 0, + /* bf6 - */ 0, + /* bf7 - */ 0, + /* bf8 - */ 0, + /* bf9 - */ 0, + /* bfa - */ 0, + /* bfb - */ 0, + /* bfc - */ 0, + /* bfd - */ 0, + /* bfe - */ 0, + /* bff - */ 0, + /* c00 - */ 0, + /* c01 - */ 0, + /* c02 - */ 0, + /* c03 - */ 0, + /* c04 - */ 0, + /* c05 - */ 0, + /* c06 - */ 0, + /* c07 - */ 0, + /* c08 - */ 0, + /* c09 - */ 0, + /* c0a - */ 0, + /* c0b - */ 0, + /* c0c - */ 0, + /* c0d - */ 0, + /* c0e - */ 0, + /* c0f - */ 0, + /* c10 - */ 0, + /* c11 - */ 0, + /* c12 - */ 0, + /* c13 - */ 0, + /* c14 - */ 0, + /* c15 - */ 0, + /* c16 - */ 0, + /* c17 - */ 0, + /* c18 - */ 0, + /* c19 - */ 0, + /* c1a - */ 0, + /* c1b - */ 0, + /* c1c - */ 0, + /* c1d - */ 0, + /* c1e - */ 0, + /* c1f - */ 0, + /* c20 - */ 0, + /* c21 - */ 0, + /* c22 - */ 0, + /* c23 - */ 0, + /* c24 - */ 0, + /* c25 - */ 0, + /* c26 - */ 0, + /* c27 - */ 0, + /* c28 - */ 0, + /* c29 - */ 0, + /* c2a - */ 0, + /* c2b - */ 0, + /* c2c - */ 0, + /* c2d - */ 0, + /* c2e - */ 0, + /* c2f - */ 0, + /* c30 - */ 0, + /* c31 - */ 0, + /* c32 - */ 0, + /* c33 - */ 0, + /* c34 - */ 0, + /* c35 - */ 0, + /* c36 - */ 0, + /* c37 - */ 0, + /* c38 - */ 0, + /* c39 - */ 0, + /* c3a - */ 0, + /* c3b - */ 0, + /* c3c - */ 0, + /* c3d - */ 0, + /* c3e - */ 0, + /* c3f - */ 0, + /* c40 - */ 0, + /* c41 - */ 0, + /* c42 - */ 0, + /* c43 - */ 0, + /* c44 - */ 0, + /* c45 - */ 0, + /* c46 - */ 0, + /* c47 - */ 0, + /* c48 - */ 0, + /* c49 - */ 0, + /* c4a - */ 0, + /* c4b - */ 0, + /* c4c - */ 0, + /* c4d - */ 0, + /* c4e - */ 0, + /* c4f - */ 0, + /* c50 - */ 0, + /* c51 - */ 0, + /* c52 - */ 0, + /* c53 - */ 0, + /* c54 - */ 0, + /* c55 - _66_0F_7C */ 0x23fe, + /* c56 - */ 0, + /* c57 - _F2_0F_7C */ 0x23ff, + /* c58 - */ 0, + /* c59 - _V_66_0F_7C */ 0x4087, + /* c5a - */ 0, + /* c5b - _V_F2_0F_7C */ 0x4088, + /* c5c - */ 0, + /* c5d - */ 0, + /* c5e - */ 0, + /* c5f - */ 0, + /* c60 - */ 0, + /* c61 - _66_0F_7D */ 0x2400, + /* c62 - */ 0, + /* c63 - _F2_0F_7D */ 0x2401, + /* c64 - */ 0, + /* c65 - _V_66_0F_7D */ 0x4089, + /* c66 - */ 0, + /* c67 - _V_F2_0F_7D */ 0x408a, + /* c68 - */ 0, + /* c69 - */ 0, + /* c6a - */ 0, + /* c6b - */ 0, + /* c6c - _0F_7E */ 0x408b, + /* c6d - _66_0F_7E */ 0x408c, + /* c6e - _F3_0F_7E */ 0x2402, + /* c6f - */ 0, + /* c70 - */ 0, + /* c71 - _V_66_0F_7E */ 0x408d, + /* c72 - _V_F3_0F_7E */ 0x408e, + /* c73 - */ 0, + /* c74 - */ 0, + /* c75 - */ 0, + /* c76 - */ 0, + /* c77 - */ 0, + /* c78 - _0F_7F */ 0x2403, + /* c79 - _66_0F_7F */ 0x2404, + /* c7a - _F3_0F_7F */ 0x2405, + /* c7b - */ 0, + /* c7c - */ 0, + /* c7d - _V_66_0F_7F */ 0x408f, + /* c7e - _V_F3_0F_7F */ 0x4090, + /* c7f - */ 0, + /* c80 - */ 0, + /* c81 - */ 0, + /* c82 - */ 0, + /* c83 - */ 0, + /* c84 - _0F_AE_00 */ 0xd5fc, + /* c85 - _0F_AE_01 */ 0xd608, + /* c86 - _0F_AE_02 */ 0xd614, + /* c87 - _0F_AE_03 */ 0xd620, + /* c88 - _0F_AE_04 */ 0x4091, + /* c89 - _0F_AE_05 */ 0x4092, + /* c8a - _0F_AE_06 */ 0x4093, + /* c8b - _0F_AE_07 */ 0x4094, + /* c8c - */ 0, + /* c8d - */ 0, + /* c8e - _F3_0F_B8 */ 0x2406, + /* c8f - */ 0, + /* c90 - */ 0, + /* c91 - */ 0, + /* c92 - */ 0, + /* c93 - */ 0, + /* c94 - */ 0, + /* c95 - */ 0, + /* c96 - */ 0, + /* c97 - */ 0, + /* c98 - */ 0, + /* c99 - */ 0, + /* c9a - */ 0, + /* c9b - */ 0, + /* c9c - _0F_BA_04 */ 0x2407, + /* c9d - _0F_BA_05 */ 0x2408, + /* c9e - _0F_BA_06 */ 0x2409, + /* c9f - _0F_BA_07 */ 0x240a, + /* ca0 - _0F_BC */ 0x240b, + /* ca1 - */ 0, + /* ca2 - _F3_0F_BC */ 0x240c, + /* ca3 - */ 0, + /* ca4 - */ 0, + /* ca5 - */ 0, + /* ca6 - */ 0, + /* ca7 - */ 0, + /* ca8 - */ 0, + /* ca9 - */ 0, + /* caa - */ 0, + /* cab - */ 0, + /* cac - _0F_BD */ 0x240d, + /* cad - */ 0, + /* cae - _F3_0F_BD */ 0x240e, + /* caf - */ 0, + /* cb0 - */ 0, + /* cb1 - */ 0, + /* cb2 - */ 0, + /* cb3 - */ 0, + /* cb4 - */ 0, + /* cb5 - */ 0, + /* cb6 - */ 0, + /* cb7 - */ 0, + /* cb8 - _0F_C2 */ 0x4095, + /* cb9 - _66_0F_C2 */ 0x4096, + /* cba - _F3_0F_C2 */ 0x4097, + /* cbb - _F2_0F_C2 */ 0x4098, + /* cbc - _V_0F_C2 */ 0x4099, + /* cbd - _V_66_0F_C2 */ 0x409a, + /* cbe - _V_F3_0F_C2 */ 0x409b, + /* cbf - _V_F2_0F_C2 */ 0x409c, + /* cc0 - */ 0, + /* cc1 - */ 0, + /* cc2 - */ 0, + /* cc3 - */ 0, + /* cc4 - _0F_C4 */ 0x409d, + /* cc5 - _66_0F_C4 */ 0x409e, + /* cc6 - */ 0, + /* cc7 - */ 0, + /* cc8 - */ 0, + /* cc9 - _V_66_0F_C4 */ 0x409f, + /* cca - */ 0, + /* ccb - */ 0, + /* ccc - */ 0, + /* ccd - */ 0, + /* cce - */ 0, + /* ccf - */ 0, + /* cd0 - _0F_C5 */ 0x40a0, + /* cd1 - _66_0F_C5 */ 0x40a1, + /* cd2 - */ 0, + /* cd3 - */ 0, + /* cd4 - */ 0, + /* cd5 - _V_66_0F_C5 */ 0x40a2, + /* cd6 - */ 0, + /* cd7 - */ 0, + /* cd8 - */ 0, + /* cd9 - */ 0, + /* cda - */ 0, + /* cdb - */ 0, + /* cdc - _0F_C6 */ 0x40a3, + /* cdd - _66_0F_C6 */ 0x40a4, + /* cde - */ 0, + /* cdf - */ 0, + /* ce0 - _V_0F_C6 */ 0x40a5, + /* ce1 - _V_66_0F_C6 */ 0x40a6, + /* ce2 - */ 0, + /* ce3 - */ 0, + /* ce4 - */ 0, + /* ce5 - */ 0, + /* ce6 - */ 0, + /* ce7 - */ 0, + /* ce8 - */ 0, + /* ce9 - _0F_C7_01 */ 0x40a7, + /* cea - */ 0, + /* ceb - */ 0, + /* cec - */ 0, + /* ced - */ 0, + /* cee - _0F_C7_06 */ 0xd62c, + /* cef - _0F_C7_07 */ 0x240f, + /* cf0 - */ 0, + /* cf1 - _66_0F_D0 */ 0x2410, + /* cf2 - */ 0, + /* cf3 - _F2_0F_D0 */ 0x2411, + /* cf4 - */ 0, + /* cf5 - _V_66_0F_D0 */ 0x40a8, + /* cf6 - */ 0, + /* cf7 - _V_F2_0F_D0 */ 0x40a9, + /* cf8 - */ 0, + /* cf9 - */ 0, + /* cfa - */ 0, + /* cfb - */ 0, + /* cfc - _0F_D1 */ 0x2412, + /* cfd - _66_0F_D1 */ 0x2413, + /* cfe - */ 0, + /* cff - */ 0, + /* d00 - */ 0, + /* d01 - _V_66_0F_D1 */ 0x40aa, + /* d02 - */ 0, + /* d03 - */ 0, + /* d04 - */ 0, + /* d05 - */ 0, + /* d06 - */ 0, + /* d07 - */ 0, + /* d08 - _0F_D2 */ 0x2414, + /* d09 - _66_0F_D2 */ 0x2415, + /* d0a - */ 0, + /* d0b - */ 0, + /* d0c - */ 0, + /* d0d - _V_66_0F_D2 */ 0x40ab, + /* d0e - */ 0, + /* d0f - */ 0, + /* d10 - */ 0, + /* d11 - */ 0, + /* d12 - */ 0, + /* d13 - */ 0, + /* d14 - _0F_D3 */ 0x2416, + /* d15 - _66_0F_D3 */ 0x2417, + /* d16 - */ 0, + /* d17 - */ 0, + /* d18 - */ 0, + /* d19 - _V_66_0F_D3 */ 0x40ac, + /* d1a - */ 0, + /* d1b - */ 0, + /* d1c - */ 0, + /* d1d - */ 0, + /* d1e - */ 0, + /* d1f - */ 0, + /* d20 - _0F_D4 */ 0x2418, + /* d21 - _66_0F_D4 */ 0x2419, + /* d22 - */ 0, + /* d23 - */ 0, + /* d24 - */ 0, + /* d25 - _V_66_0F_D4 */ 0x40ad, + /* d26 - */ 0, + /* d27 - */ 0, + /* d28 - */ 0, + /* d29 - */ 0, + /* d2a - */ 0, + /* d2b - */ 0, + /* d2c - _0F_D5 */ 0x241a, + /* d2d - _66_0F_D5 */ 0x241b, + /* d2e - */ 0, + /* d2f - */ 0, + /* d30 - */ 0, + /* d31 - _V_66_0F_D5 */ 0x40ae, + /* d32 - */ 0, + /* d33 - */ 0, + /* d34 - */ 0, + /* d35 - */ 0, + /* d36 - */ 0, + /* d37 - */ 0, + /* d38 - */ 0, + /* d39 - _66_0F_D6 */ 0x241c, + /* d3a - _F3_0F_D6 */ 0x241d, + /* d3b - _F2_0F_D6 */ 0x241e, + /* d3c - */ 0, + /* d3d - _V_66_0F_D6 */ 0x40af, + /* d3e - */ 0, + /* d3f - */ 0, + /* d40 - */ 0, + /* d41 - */ 0, + /* d42 - */ 0, + /* d43 - */ 0, + /* d44 - _0F_D7 */ 0x241f, + /* d45 - _66_0F_D7 */ 0x2420, + /* d46 - */ 0, + /* d47 - */ 0, + /* d48 - */ 0, + /* d49 - _V_66_0F_D7 */ 0x40b0, + /* d4a - */ 0, + /* d4b - */ 0, + /* d4c - */ 0, + /* d4d - */ 0, + /* d4e - */ 0, + /* d4f - */ 0, + /* d50 - _0F_D8 */ 0x2421, + /* d51 - _66_0F_D8 */ 0x2422, + /* d52 - */ 0, + /* d53 - */ 0, + /* d54 - */ 0, + /* d55 - _V_66_0F_D8 */ 0x40b1, + /* d56 - */ 0, + /* d57 - */ 0, + /* d58 - */ 0, + /* d59 - */ 0, + /* d5a - */ 0, + /* d5b - */ 0, + /* d5c - _0F_D9 */ 0x2423, + /* d5d - _66_0F_D9 */ 0x2424, + /* d5e - */ 0, + /* d5f - */ 0, + /* d60 - */ 0, + /* d61 - _V_66_0F_D9 */ 0x40b2, + /* d62 - */ 0, + /* d63 - */ 0, + /* d64 - */ 0, + /* d65 - */ 0, + /* d66 - */ 0, + /* d67 - */ 0, + /* d68 - _0F_DA */ 0x2425, + /* d69 - _66_0F_DA */ 0x2426, + /* d6a - */ 0, + /* d6b - */ 0, + /* d6c - */ 0, + /* d6d - _V_66_0F_DA */ 0x40b3, + /* d6e - */ 0, + /* d6f - */ 0, + /* d70 - */ 0, + /* d71 - */ 0, + /* d72 - */ 0, + /* d73 - */ 0, + /* d74 - _0F_DB */ 0x2427, + /* d75 - _66_0F_DB */ 0x2428, + /* d76 - */ 0, + /* d77 - */ 0, + /* d78 - */ 0, + /* d79 - _V_66_0F_DB */ 0x40b4, + /* d7a - */ 0, + /* d7b - */ 0, + /* d7c - */ 0, + /* d7d - */ 0, + /* d7e - */ 0, + /* d7f - */ 0, + /* d80 - _0F_DC */ 0x2429, + /* d81 - _66_0F_DC */ 0x242a, + /* d82 - */ 0, + /* d83 - */ 0, + /* d84 - */ 0, + /* d85 - _V_66_0F_DC */ 0x40b5, + /* d86 - */ 0, + /* d87 - */ 0, + /* d88 - */ 0, + /* d89 - */ 0, + /* d8a - */ 0, + /* d8b - */ 0, + /* d8c - _0F_DD */ 0x242b, + /* d8d - _66_0F_DD */ 0x242c, + /* d8e - */ 0, + /* d8f - */ 0, + /* d90 - */ 0, + /* d91 - _V_66_0F_DD */ 0x40b6, + /* d92 - */ 0, + /* d93 - */ 0, + /* d94 - */ 0, + /* d95 - */ 0, + /* d96 - */ 0, + /* d97 - */ 0, + /* d98 - _0F_DE */ 0x242d, + /* d99 - _66_0F_DE */ 0x242e, + /* d9a - */ 0, + /* d9b - */ 0, + /* d9c - */ 0, + /* d9d - _V_66_0F_DE */ 0x40b7, + /* d9e - */ 0, + /* d9f - */ 0, + /* da0 - */ 0, + /* da1 - */ 0, + /* da2 - */ 0, + /* da3 - */ 0, + /* da4 - _0F_DF */ 0x242f, + /* da5 - _66_0F_DF */ 0x2430, + /* da6 - */ 0, + /* da7 - */ 0, + /* da8 - */ 0, + /* da9 - _V_66_0F_DF */ 0x40b8, + /* daa - */ 0, + /* dab - */ 0, + /* dac - */ 0, + /* dad - */ 0, + /* dae - */ 0, + /* daf - */ 0, + /* db0 - _0F_E0 */ 0x2431, + /* db1 - _66_0F_E0 */ 0x2432, + /* db2 - */ 0, + /* db3 - */ 0, + /* db4 - */ 0, + /* db5 - _V_66_0F_E0 */ 0x40b9, + /* db6 - */ 0, + /* db7 - */ 0, + /* db8 - */ 0, + /* db9 - */ 0, + /* dba - */ 0, + /* dbb - */ 0, + /* dbc - _0F_E1 */ 0x2433, + /* dbd - _66_0F_E1 */ 0x2434, + /* dbe - */ 0, + /* dbf - */ 0, + /* dc0 - */ 0, + /* dc1 - _V_66_0F_E1 */ 0x40ba, + /* dc2 - */ 0, + /* dc3 - */ 0, + /* dc4 - */ 0, + /* dc5 - */ 0, + /* dc6 - */ 0, + /* dc7 - */ 0, + /* dc8 - _0F_E2 */ 0x2435, + /* dc9 - _66_0F_E2 */ 0x2436, + /* dca - */ 0, + /* dcb - */ 0, + /* dcc - */ 0, + /* dcd - _V_66_0F_E2 */ 0x40bb, + /* dce - */ 0, + /* dcf - */ 0, + /* dd0 - */ 0, + /* dd1 - */ 0, + /* dd2 - */ 0, + /* dd3 - */ 0, + /* dd4 - _0F_E3 */ 0x2437, + /* dd5 - _66_0F_E3 */ 0x2438, + /* dd6 - */ 0, + /* dd7 - */ 0, + /* dd8 - */ 0, + /* dd9 - _V_66_0F_E3 */ 0x40bc, + /* dda - */ 0, + /* ddb - */ 0, + /* ddc - */ 0, + /* ddd - */ 0, + /* dde - */ 0, + /* ddf - */ 0, + /* de0 - _0F_E4 */ 0x2439, + /* de1 - _66_0F_E4 */ 0x243a, + /* de2 - */ 0, + /* de3 - */ 0, + /* de4 - */ 0, + /* de5 - _V_66_0F_E4 */ 0x40bd, + /* de6 - */ 0, + /* de7 - */ 0, + /* de8 - */ 0, + /* de9 - */ 0, + /* dea - */ 0, + /* deb - */ 0, + /* dec - _0F_E5 */ 0x243b, + /* ded - _66_0F_E5 */ 0x243c, + /* dee - */ 0, + /* def - */ 0, + /* df0 - */ 0, + /* df1 - _V_66_0F_E5 */ 0x40be, + /* df2 - */ 0, + /* df3 - */ 0, + /* df4 - */ 0, + /* df5 - */ 0, + /* df6 - */ 0, + /* df7 - */ 0, + /* df8 - */ 0, + /* df9 - _66_0F_E6 */ 0x243d, + /* dfa - _F3_0F_E6 */ 0x243e, + /* dfb - _F2_0F_E6 */ 0x243f, + /* dfc - */ 0, + /* dfd - _V_66_0F_E6 */ 0x40bf, + /* dfe - _V_F3_0F_E6 */ 0x40c0, + /* dff - _V_F2_0F_E6 */ 0x40c1, + /* e00 - */ 0, + /* e01 - */ 0, + /* e02 - */ 0, + /* e03 - */ 0, + /* e04 - _0F_E7 */ 0x2440, + /* e05 - _66_0F_E7 */ 0x2441, + /* e06 - */ 0, + /* e07 - */ 0, + /* e08 - */ 0, + /* e09 - _V_66_0F_E7 */ 0x40c2, + /* e0a - */ 0, + /* e0b - */ 0, + /* e0c - */ 0, + /* e0d - */ 0, + /* e0e - */ 0, + /* e0f - */ 0, + /* e10 - _0F_E8 */ 0x2442, + /* e11 - _66_0F_E8 */ 0x2443, + /* e12 - */ 0, + /* e13 - */ 0, + /* e14 - */ 0, + /* e15 - _V_66_0F_E8 */ 0x40c3, + /* e16 - */ 0, + /* e17 - */ 0, + /* e18 - */ 0, + /* e19 - */ 0, + /* e1a - */ 0, + /* e1b - */ 0, + /* e1c - _0F_E9 */ 0x2444, + /* e1d - _66_0F_E9 */ 0x2445, + /* e1e - */ 0, + /* e1f - */ 0, + /* e20 - */ 0, + /* e21 - _V_66_0F_E9 */ 0x40c4, + /* e22 - */ 0, + /* e23 - */ 0, + /* e24 - */ 0, + /* e25 - */ 0, + /* e26 - */ 0, + /* e27 - */ 0, + /* e28 - _0F_EA */ 0x2446, + /* e29 - _66_0F_EA */ 0x2447, + /* e2a - */ 0, + /* e2b - */ 0, + /* e2c - */ 0, + /* e2d - _V_66_0F_EA */ 0x40c5, + /* e2e - */ 0, + /* e2f - */ 0, + /* e30 - */ 0, + /* e31 - */ 0, + /* e32 - */ 0, + /* e33 - */ 0, + /* e34 - _0F_EB */ 0x2448, + /* e35 - _66_0F_EB */ 0x2449, + /* e36 - */ 0, + /* e37 - */ 0, + /* e38 - */ 0, + /* e39 - _V_66_0F_EB */ 0x40c6, + /* e3a - */ 0, + /* e3b - */ 0, + /* e3c - */ 0, + /* e3d - */ 0, + /* e3e - */ 0, + /* e3f - */ 0, + /* e40 - _0F_EC */ 0x244a, + /* e41 - _66_0F_EC */ 0x244b, + /* e42 - */ 0, + /* e43 - */ 0, + /* e44 - */ 0, + /* e45 - _V_66_0F_EC */ 0x40c7, + /* e46 - */ 0, + /* e47 - */ 0, + /* e48 - */ 0, + /* e49 - */ 0, + /* e4a - */ 0, + /* e4b - */ 0, + /* e4c - _0F_ED */ 0x244c, + /* e4d - _66_0F_ED */ 0x244d, + /* e4e - */ 0, + /* e4f - */ 0, + /* e50 - */ 0, + /* e51 - _V_66_0F_ED */ 0x40c8, + /* e52 - */ 0, + /* e53 - */ 0, + /* e54 - */ 0, + /* e55 - */ 0, + /* e56 - */ 0, + /* e57 - */ 0, + /* e58 - _0F_EE */ 0x244e, + /* e59 - _66_0F_EE */ 0x244f, + /* e5a - */ 0, + /* e5b - */ 0, + /* e5c - */ 0, + /* e5d - _V_66_0F_EE */ 0x40c9, + /* e5e - */ 0, + /* e5f - */ 0, + /* e60 - */ 0, + /* e61 - */ 0, + /* e62 - */ 0, + /* e63 - */ 0, + /* e64 - _0F_EF */ 0x2450, + /* e65 - _66_0F_EF */ 0x2451, + /* e66 - */ 0, + /* e67 - */ 0, + /* e68 - */ 0, + /* e69 - _V_66_0F_EF */ 0x40ca, + /* e6a - */ 0, + /* e6b - */ 0, + /* e6c - */ 0, + /* e6d - */ 0, + /* e6e - */ 0, + /* e6f - */ 0, + /* e70 - */ 0, + /* e71 - */ 0, + /* e72 - */ 0, + /* e73 - _F2_0F_F0 */ 0x2452, + /* e74 - */ 0, + /* e75 - */ 0, + /* e76 - */ 0, + /* e77 - _V_F2_0F_F0 */ 0x40cb, + /* e78 - */ 0, + /* e79 - */ 0, + /* e7a - */ 0, + /* e7b - */ 0, + /* e7c - _0F_F1 */ 0x2453, + /* e7d - _66_0F_F1 */ 0x2454, + /* e7e - */ 0, + /* e7f - */ 0, + /* e80 - */ 0, + /* e81 - _V_66_0F_F1 */ 0x40cc, + /* e82 - */ 0, + /* e83 - */ 0, + /* e84 - */ 0, + /* e85 - */ 0, + /* e86 - */ 0, + /* e87 - */ 0, + /* e88 - _0F_F2 */ 0x2455, + /* e89 - _66_0F_F2 */ 0x2456, + /* e8a - */ 0, + /* e8b - */ 0, + /* e8c - */ 0, + /* e8d - _V_66_0F_F2 */ 0x40cd, + /* e8e - */ 0, + /* e8f - */ 0, + /* e90 - */ 0, + /* e91 - */ 0, + /* e92 - */ 0, + /* e93 - */ 0, + /* e94 - _0F_F3 */ 0x2457, + /* e95 - _66_0F_F3 */ 0x2458, + /* e96 - */ 0, + /* e97 - */ 0, + /* e98 - */ 0, + /* e99 - _V_66_0F_F3 */ 0x40ce, + /* e9a - */ 0, + /* e9b - */ 0, + /* e9c - */ 0, + /* e9d - */ 0, + /* e9e - */ 0, + /* e9f - */ 0, + /* ea0 - _0F_F4 */ 0x2459, + /* ea1 - _66_0F_F4 */ 0x245a, + /* ea2 - */ 0, + /* ea3 - */ 0, + /* ea4 - */ 0, + /* ea5 - _V_66_0F_F4 */ 0x40cf, + /* ea6 - */ 0, + /* ea7 - */ 0, + /* ea8 - */ 0, + /* ea9 - */ 0, + /* eaa - */ 0, + /* eab - */ 0, + /* eac - _0F_F5 */ 0x245b, + /* ead - _66_0F_F5 */ 0x245c, + /* eae - */ 0, + /* eaf - */ 0, + /* eb0 - */ 0, + /* eb1 - _V_66_0F_F5 */ 0x40d0, + /* eb2 - */ 0, + /* eb3 - */ 0, + /* eb4 - */ 0, + /* eb5 - */ 0, + /* eb6 - */ 0, + /* eb7 - */ 0, + /* eb8 - _0F_F6 */ 0x245d, + /* eb9 - _66_0F_F6 */ 0x245e, + /* eba - */ 0, + /* ebb - */ 0, + /* ebc - */ 0, + /* ebd - _V_66_0F_F6 */ 0x40d1, + /* ebe - */ 0, + /* ebf - */ 0, + /* ec0 - */ 0, + /* ec1 - */ 0, + /* ec2 - */ 0, + /* ec3 - */ 0, + /* ec4 - _0F_F7 */ 0x245f, + /* ec5 - _66_0F_F7 */ 0x2460, + /* ec6 - */ 0, + /* ec7 - */ 0, + /* ec8 - */ 0, + /* ec9 - _V_66_0F_F7 */ 0x40d2, + /* eca - */ 0, + /* ecb - */ 0, + /* ecc - */ 0, + /* ecd - */ 0, + /* ece - */ 0, + /* ecf - */ 0, + /* ed0 - _0F_F8 */ 0x2461, + /* ed1 - _66_0F_F8 */ 0x2462, + /* ed2 - */ 0, + /* ed3 - */ 0, + /* ed4 - */ 0, + /* ed5 - _V_66_0F_F8 */ 0x40d3, + /* ed6 - */ 0, + /* ed7 - */ 0, + /* ed8 - */ 0, + /* ed9 - */ 0, + /* eda - */ 0, + /* edb - */ 0, + /* edc - _0F_F9 */ 0x2463, + /* edd - _66_0F_F9 */ 0x2464, + /* ede - */ 0, + /* edf - */ 0, + /* ee0 - */ 0, + /* ee1 - _V_66_0F_F9 */ 0x40d4, + /* ee2 - */ 0, + /* ee3 - */ 0, + /* ee4 - */ 0, + /* ee5 - */ 0, + /* ee6 - */ 0, + /* ee7 - */ 0, + /* ee8 - _0F_FA */ 0x2465, + /* ee9 - _66_0F_FA */ 0x2466, + /* eea - */ 0, + /* eeb - */ 0, + /* eec - */ 0, + /* eed - _V_66_0F_FA */ 0x40d5, + /* eee - */ 0, + /* eef - */ 0, + /* ef0 - */ 0, + /* ef1 - */ 0, + /* ef2 - */ 0, + /* ef3 - */ 0, + /* ef4 - _0F_FB */ 0x2467, + /* ef5 - _66_0F_FB */ 0x2468, + /* ef6 - */ 0, + /* ef7 - */ 0, + /* ef8 - */ 0, + /* ef9 - _V_66_0F_FB */ 0x40d6, + /* efa - */ 0, + /* efb - */ 0, + /* efc - */ 0, + /* efd - */ 0, + /* efe - */ 0, + /* eff - */ 0, + /* f00 - _0F_FC */ 0x2469, + /* f01 - _66_0F_FC */ 0x246a, + /* f02 - */ 0, + /* f03 - */ 0, + /* f04 - */ 0, + /* f05 - _V_66_0F_FC */ 0x40d7, + /* f06 - */ 0, + /* f07 - */ 0, + /* f08 - */ 0, + /* f09 - */ 0, + /* f0a - */ 0, + /* f0b - */ 0, + /* f0c - _0F_FD */ 0x246b, + /* f0d - _66_0F_FD */ 0x246c, + /* f0e - */ 0, + /* f0f - */ 0, + /* f10 - */ 0, + /* f11 - _V_66_0F_FD */ 0x40d8, + /* f12 - */ 0, + /* f13 - */ 0, + /* f14 - */ 0, + /* f15 - */ 0, + /* f16 - */ 0, + /* f17 - */ 0, + /* f18 - _0F_FE */ 0x246d, + /* f19 - _66_0F_FE */ 0x246e, + /* f1a - */ 0, + /* f1b - */ 0, + /* f1c - */ 0, + /* f1d - _V_66_0F_FE */ 0x40d9, + /* f1e - */ 0, + /* f1f - */ 0, + /* f20 - */ 0, + /* f21 - */ 0, + /* f22 - */ 0, + /* f23 - */ 0, + /* f24 - _D9_06 */ 0x246f, + /* f25 - _9B_D9_06 */ 0x2470, + /* f26 - */ 0, + /* f27 - */ 0, + /* f28 - */ 0, + /* f29 - */ 0, + /* f2a - */ 0, + /* f2b - */ 0, + /* f2c - */ 0, + /* f2d - */ 0, + /* f2e - */ 0, + /* f2f - */ 0, + /* f30 - _D9_07 */ 0x2471, + /* f31 - _9B_D9_07 */ 0x2472, + /* f32 - */ 0, + /* f33 - */ 0, + /* f34 - */ 0, + /* f35 - */ 0, + /* f36 - */ 0, + /* f37 - */ 0, + /* f38 - */ 0, + /* f39 - */ 0, + /* f3a - */ 0, + /* f3b - */ 0, + /* f3c - _DB_E2 */ 0x2473, + /* f3d - _9B_DB_E2 */ 0x2474, + /* f3e - */ 0, + /* f3f - */ 0, + /* f40 - */ 0, + /* f41 - */ 0, + /* f42 - */ 0, + /* f43 - */ 0, + /* f44 - */ 0, + /* f45 - */ 0, + /* f46 - */ 0, + /* f47 - */ 0, + /* f48 - _DB_E3 */ 0x2475, + /* f49 - _9B_DB_E3 */ 0x2476, + /* f4a - */ 0, + /* f4b - */ 0, + /* f4c - */ 0, + /* f4d - */ 0, + /* f4e - */ 0, + /* f4f - */ 0, + /* f50 - */ 0, + /* f51 - */ 0, + /* f52 - */ 0, + /* f53 - */ 0, + /* f54 - _DD_06 */ 0x2477, + /* f55 - _9B_DD_06 */ 0x2478, + /* f56 - */ 0, + /* f57 - */ 0, + /* f58 - */ 0, + /* f59 - */ 0, + /* f5a - */ 0, + /* f5b - */ 0, + /* f5c - */ 0, + /* f5d - */ 0, + /* f5e - */ 0, + /* f5f - */ 0, + /* f60 - _DD_07 */ 0x2479, + /* f61 - _9B_DD_07 */ 0x247a, + /* f62 - */ 0, + /* f63 - */ 0, + /* f64 - */ 0, + /* f65 - */ 0, + /* f66 - */ 0, + /* f67 - */ 0, + /* f68 - */ 0, + /* f69 - */ 0, + /* f6a - */ 0, + /* f6b - */ 0, + /* f6c - _DF_E0 */ 0x247b, + /* f6d - _9B_DF_E0 */ 0x247c, + /* f6e - */ 0, + /* f6f - */ 0, + /* f70 - */ 0, + /* f71 - */ 0, + /* f72 - */ 0, + /* f73 - */ 0, + /* f74 - */ 0, + /* f75 - */ 0, + /* f76 - */ 0, + /* f77 - */ 0, + /* f78 - _0F_38_00 */ 0x247d, + /* f79 - _66_0F_38_00 */ 0x247e, + /* f7a - */ 0, + /* f7b - */ 0, + /* f7c - */ 0, + /* f7d - _V_66_0F_38_00 */ 0x40da, + /* f7e - */ 0, + /* f7f - */ 0, + /* f80 - */ 0, + /* f81 - */ 0, + /* f82 - */ 0, + /* f83 - */ 0, + /* f84 - _0F_38_01 */ 0x247f, + /* f85 - _66_0F_38_01 */ 0x2480, + /* f86 - */ 0, + /* f87 - */ 0, + /* f88 - */ 0, + /* f89 - _V_66_0F_38_01 */ 0x40db, + /* f8a - */ 0, + /* f8b - */ 0, + /* f8c - */ 0, + /* f8d - */ 0, + /* f8e - */ 0, + /* f8f - */ 0, + /* f90 - _0F_38_02 */ 0x2481, + /* f91 - _66_0F_38_02 */ 0x2482, + /* f92 - */ 0, + /* f93 - */ 0, + /* f94 - */ 0, + /* f95 - _V_66_0F_38_02 */ 0x40dc, + /* f96 - */ 0, + /* f97 - */ 0, + /* f98 - */ 0, + /* f99 - */ 0, + /* f9a - */ 0, + /* f9b - */ 0, + /* f9c - _0F_38_03 */ 0x2483, + /* f9d - _66_0F_38_03 */ 0x2484, + /* f9e - */ 0, + /* f9f - */ 0, + /* fa0 - */ 0, + /* fa1 - _V_66_0F_38_03 */ 0x40dd, + /* fa2 - */ 0, + /* fa3 - */ 0, + /* fa4 - */ 0, + /* fa5 - */ 0, + /* fa6 - */ 0, + /* fa7 - */ 0, + /* fa8 - _0F_38_04 */ 0x2485, + /* fa9 - _66_0F_38_04 */ 0x2486, + /* faa - */ 0, + /* fab - */ 0, + /* fac - */ 0, + /* fad - _V_66_0F_38_04 */ 0x40de, + /* fae - */ 0, + /* faf - */ 0, + /* fb0 - */ 0, + /* fb1 - */ 0, + /* fb2 - */ 0, + /* fb3 - */ 0, + /* fb4 - _0F_38_05 */ 0x2487, + /* fb5 - _66_0F_38_05 */ 0x2488, + /* fb6 - */ 0, + /* fb7 - */ 0, + /* fb8 - */ 0, + /* fb9 - _V_66_0F_38_05 */ 0x40df, + /* fba - */ 0, + /* fbb - */ 0, + /* fbc - */ 0, + /* fbd - */ 0, + /* fbe - */ 0, + /* fbf - */ 0, + /* fc0 - _0F_38_06 */ 0x2489, + /* fc1 - _66_0F_38_06 */ 0x248a, + /* fc2 - */ 0, + /* fc3 - */ 0, + /* fc4 - */ 0, + /* fc5 - _V_66_0F_38_06 */ 0x40e0, + /* fc6 - */ 0, + /* fc7 - */ 0, + /* fc8 - */ 0, + /* fc9 - */ 0, + /* fca - */ 0, + /* fcb - */ 0, + /* fcc - _0F_38_07 */ 0x248b, + /* fcd - _66_0F_38_07 */ 0x248c, + /* fce - */ 0, + /* fcf - */ 0, + /* fd0 - */ 0, + /* fd1 - _V_66_0F_38_07 */ 0x40e1, + /* fd2 - */ 0, + /* fd3 - */ 0, + /* fd4 - */ 0, + /* fd5 - */ 0, + /* fd6 - */ 0, + /* fd7 - */ 0, + /* fd8 - _0F_38_08 */ 0x248d, + /* fd9 - _66_0F_38_08 */ 0x248e, + /* fda - */ 0, + /* fdb - */ 0, + /* fdc - */ 0, + /* fdd - _V_66_0F_38_08 */ 0x40e2, + /* fde - */ 0, + /* fdf - */ 0, + /* fe0 - */ 0, + /* fe1 - */ 0, + /* fe2 - */ 0, + /* fe3 - */ 0, + /* fe4 - _0F_38_09 */ 0x248f, + /* fe5 - _66_0F_38_09 */ 0x2490, + /* fe6 - */ 0, + /* fe7 - */ 0, + /* fe8 - */ 0, + /* fe9 - _V_66_0F_38_09 */ 0x40e3, + /* fea - */ 0, + /* feb - */ 0, + /* fec - */ 0, + /* fed - */ 0, + /* fee - */ 0, + /* fef - */ 0, + /* ff0 - _0F_38_0A */ 0x2491, + /* ff1 - _66_0F_38_0A */ 0x2492, + /* ff2 - */ 0, + /* ff3 - */ 0, + /* ff4 - */ 0, + /* ff5 - _V_66_0F_38_0A */ 0x40e4, + /* ff6 - */ 0, + /* ff7 - */ 0, + /* ff8 - */ 0, + /* ff9 - */ 0, + /* ffa - */ 0, + /* ffb - */ 0, + /* ffc - _0F_38_0B */ 0x2493, + /* ffd - _66_0F_38_0B */ 0x2494, + /* ffe - */ 0, + /* fff - */ 0, + /* 1000 - */ 0, + /* 1001 - _V_66_0F_38_0B */ 0x40e5, + /* 1002 - */ 0, + /* 1003 - */ 0, + /* 1004 - */ 0, + /* 1005 - */ 0, + /* 1006 - */ 0, + /* 1007 - */ 0, + /* 1008 - */ 0, + /* 1009 - */ 0, + /* 100a - */ 0, + /* 100b - */ 0, + /* 100c - */ 0, + /* 100d - _V_66_0F_38_0C */ 0x40e6, + /* 100e - */ 0, + /* 100f - */ 0, + /* 1010 - */ 0, + /* 1011 - */ 0, + /* 1012 - */ 0, + /* 1013 - */ 0, + /* 1014 - */ 0, + /* 1015 - */ 0, + /* 1016 - */ 0, + /* 1017 - */ 0, + /* 1018 - */ 0, + /* 1019 - _V_66_0F_38_0D */ 0x40e7, + /* 101a - */ 0, + /* 101b - */ 0, + /* 101c - */ 0, + /* 101d - */ 0, + /* 101e - */ 0, + /* 101f - */ 0, + /* 1020 - */ 0, + /* 1021 - */ 0, + /* 1022 - */ 0, + /* 1023 - */ 0, + /* 1024 - */ 0, + /* 1025 - _V_66_0F_38_0E */ 0x40e8, + /* 1026 - */ 0, + /* 1027 - */ 0, + /* 1028 - */ 0, + /* 1029 - */ 0, + /* 102a - */ 0, + /* 102b - */ 0, + /* 102c - */ 0, + /* 102d - */ 0, + /* 102e - */ 0, + /* 102f - */ 0, + /* 1030 - */ 0, + /* 1031 - _V_66_0F_38_0F */ 0x40e9, + /* 1032 - */ 0, + /* 1033 - */ 0, + /* 1034 - */ 0, + /* 1035 - */ 0, + /* 1036 - */ 0, + /* 1037 - */ 0, + /* 1038 - */ 0, + /* 1039 - _66_0F_38_10 */ 0x40ea, + /* 103a - */ 0, + /* 103b - */ 0, + /* 103c - */ 0, + /* 103d - */ 0, + /* 103e - */ 0, + /* 103f - */ 0, + /* 1040 - */ 0, + /* 1041 - */ 0, + /* 1042 - */ 0, + /* 1043 - */ 0, + /* 1044 - */ 0, + /* 1045 - _66_0F_38_14 */ 0x40eb, + /* 1046 - */ 0, + /* 1047 - */ 0, + /* 1048 - */ 0, + /* 1049 - */ 0, + /* 104a - */ 0, + /* 104b - */ 0, + /* 104c - */ 0, + /* 104d - */ 0, + /* 104e - */ 0, + /* 104f - */ 0, + /* 1050 - */ 0, + /* 1051 - _66_0F_38_15 */ 0x40ec, + /* 1052 - */ 0, + /* 1053 - */ 0, + /* 1054 - */ 0, + /* 1055 - */ 0, + /* 1056 - */ 0, + /* 1057 - */ 0, + /* 1058 - */ 0, + /* 1059 - */ 0, + /* 105a - */ 0, + /* 105b - */ 0, + /* 105c - */ 0, + /* 105d - _66_0F_38_17 */ 0x2495, + /* 105e - */ 0, + /* 105f - */ 0, + /* 1060 - */ 0, + /* 1061 - _V_66_0F_38_17 */ 0x40ed, + /* 1062 - */ 0, + /* 1063 - */ 0, + /* 1064 - */ 0, + /* 1065 - */ 0, + /* 1066 - */ 0, + /* 1067 - */ 0, + /* 1068 - */ 0, + /* 1069 - */ 0, + /* 106a - */ 0, + /* 106b - */ 0, + /* 106c - */ 0, + /* 106d - _V_66_0F_38_18 */ 0x40ee, + /* 106e - */ 0, + /* 106f - */ 0, + /* 1070 - */ 0, + /* 1071 - */ 0, + /* 1072 - */ 0, + /* 1073 - */ 0, + /* 1074 - */ 0, + /* 1075 - */ 0, + /* 1076 - */ 0, + /* 1077 - */ 0, + /* 1078 - */ 0, + /* 1079 - _V_66_0F_38_19 */ 0x40ef, + /* 107a - */ 0, + /* 107b - */ 0, + /* 107c - */ 0, + /* 107d - */ 0, + /* 107e - */ 0, + /* 107f - */ 0, + /* 1080 - */ 0, + /* 1081 - */ 0, + /* 1082 - */ 0, + /* 1083 - */ 0, + /* 1084 - */ 0, + /* 1085 - _V_66_0F_38_1A */ 0x40f0, + /* 1086 - */ 0, + /* 1087 - */ 0, + /* 1088 - */ 0, + /* 1089 - */ 0, + /* 108a - */ 0, + /* 108b - */ 0, + /* 108c - _0F_38_1C */ 0x2496, + /* 108d - _66_0F_38_1C */ 0x2497, + /* 108e - */ 0, + /* 108f - */ 0, + /* 1090 - */ 0, + /* 1091 - _V_66_0F_38_1C */ 0x40f1, + /* 1092 - */ 0, + /* 1093 - */ 0, + /* 1094 - */ 0, + /* 1095 - */ 0, + /* 1096 - */ 0, + /* 1097 - */ 0, + /* 1098 - _0F_38_1D */ 0x2498, + /* 1099 - _66_0F_38_1D */ 0x2499, + /* 109a - */ 0, + /* 109b - */ 0, + /* 109c - */ 0, + /* 109d - _V_66_0F_38_1D */ 0x40f2, + /* 109e - */ 0, + /* 109f - */ 0, + /* 10a0 - */ 0, + /* 10a1 - */ 0, + /* 10a2 - */ 0, + /* 10a3 - */ 0, + /* 10a4 - _0F_38_1E */ 0x249a, + /* 10a5 - _66_0F_38_1E */ 0x249b, + /* 10a6 - */ 0, + /* 10a7 - */ 0, + /* 10a8 - */ 0, + /* 10a9 - _V_66_0F_38_1E */ 0x40f3, + /* 10aa - */ 0, + /* 10ab - */ 0, + /* 10ac - */ 0, + /* 10ad - */ 0, + /* 10ae - */ 0, + /* 10af - */ 0, + /* 10b0 - */ 0, + /* 10b1 - _66_0F_38_20 */ 0x249c, + /* 10b2 - */ 0, + /* 10b3 - */ 0, + /* 10b4 - */ 0, + /* 10b5 - _V_66_0F_38_20 */ 0x40f4, + /* 10b6 - */ 0, + /* 10b7 - */ 0, + /* 10b8 - */ 0, + /* 10b9 - */ 0, + /* 10ba - */ 0, + /* 10bb - */ 0, + /* 10bc - */ 0, + /* 10bd - _66_0F_38_21 */ 0x249d, + /* 10be - */ 0, + /* 10bf - */ 0, + /* 10c0 - */ 0, + /* 10c1 - _V_66_0F_38_21 */ 0x40f5, + /* 10c2 - */ 0, + /* 10c3 - */ 0, + /* 10c4 - */ 0, + /* 10c5 - */ 0, + /* 10c6 - */ 0, + /* 10c7 - */ 0, + /* 10c8 - */ 0, + /* 10c9 - _66_0F_38_22 */ 0x249e, + /* 10ca - */ 0, + /* 10cb - */ 0, + /* 10cc - */ 0, + /* 10cd - _V_66_0F_38_22 */ 0x40f6, + /* 10ce - */ 0, + /* 10cf - */ 0, + /* 10d0 - */ 0, + /* 10d1 - */ 0, + /* 10d2 - */ 0, + /* 10d3 - */ 0, + /* 10d4 - */ 0, + /* 10d5 - _66_0F_38_23 */ 0x249f, + /* 10d6 - */ 0, + /* 10d7 - */ 0, + /* 10d8 - */ 0, + /* 10d9 - _V_66_0F_38_23 */ 0x40f7, + /* 10da - */ 0, + /* 10db - */ 0, + /* 10dc - */ 0, + /* 10dd - */ 0, + /* 10de - */ 0, + /* 10df - */ 0, + /* 10e0 - */ 0, + /* 10e1 - _66_0F_38_24 */ 0x24a0, + /* 10e2 - */ 0, + /* 10e3 - */ 0, + /* 10e4 - */ 0, + /* 10e5 - _V_66_0F_38_24 */ 0x40f8, + /* 10e6 - */ 0, + /* 10e7 - */ 0, + /* 10e8 - */ 0, + /* 10e9 - */ 0, + /* 10ea - */ 0, + /* 10eb - */ 0, + /* 10ec - */ 0, + /* 10ed - _66_0F_38_25 */ 0x24a1, + /* 10ee - */ 0, + /* 10ef - */ 0, + /* 10f0 - */ 0, + /* 10f1 - _V_66_0F_38_25 */ 0x40f9, + /* 10f2 - */ 0, + /* 10f3 - */ 0, + /* 10f4 - */ 0, + /* 10f5 - */ 0, + /* 10f6 - */ 0, + /* 10f7 - */ 0, + /* 10f8 - */ 0, + /* 10f9 - _66_0F_38_28 */ 0x24a2, + /* 10fa - */ 0, + /* 10fb - */ 0, + /* 10fc - */ 0, + /* 10fd - _V_66_0F_38_28 */ 0x40fa, + /* 10fe - */ 0, + /* 10ff - */ 0, + /* 1100 - */ 0, + /* 1101 - */ 0, + /* 1102 - */ 0, + /* 1103 - */ 0, + /* 1104 - */ 0, + /* 1105 - _66_0F_38_29 */ 0x24a3, + /* 1106 - */ 0, + /* 1107 - */ 0, + /* 1108 - */ 0, + /* 1109 - _V_66_0F_38_29 */ 0x40fb, + /* 110a - */ 0, + /* 110b - */ 0, + /* 110c - */ 0, + /* 110d - */ 0, + /* 110e - */ 0, + /* 110f - */ 0, + /* 1110 - */ 0, + /* 1111 - _66_0F_38_2A */ 0x24a4, + /* 1112 - */ 0, + /* 1113 - */ 0, + /* 1114 - */ 0, + /* 1115 - _V_66_0F_38_2A */ 0x40fc, + /* 1116 - */ 0, + /* 1117 - */ 0, + /* 1118 - */ 0, + /* 1119 - */ 0, + /* 111a - */ 0, + /* 111b - */ 0, + /* 111c - */ 0, + /* 111d - _66_0F_38_2B */ 0x24a5, + /* 111e - */ 0, + /* 111f - */ 0, + /* 1120 - */ 0, + /* 1121 - _V_66_0F_38_2B */ 0x40fd, + /* 1122 - */ 0, + /* 1123 - */ 0, + /* 1124 - */ 0, + /* 1125 - */ 0, + /* 1126 - */ 0, + /* 1127 - */ 0, + /* 1128 - */ 0, + /* 1129 - */ 0, + /* 112a - */ 0, + /* 112b - */ 0, + /* 112c - */ 0, + /* 112d - _V_66_0F_38_2C */ 0x40fe, + /* 112e - */ 0, + /* 112f - */ 0, + /* 1130 - */ 0, + /* 1131 - */ 0, + /* 1132 - */ 0, + /* 1133 - */ 0, + /* 1134 - */ 0, + /* 1135 - */ 0, + /* 1136 - */ 0, + /* 1137 - */ 0, + /* 1138 - */ 0, + /* 1139 - _V_66_0F_38_2D */ 0x40ff, + /* 113a - */ 0, + /* 113b - */ 0, + /* 113c - */ 0, + /* 113d - */ 0, + /* 113e - */ 0, + /* 113f - */ 0, + /* 1140 - */ 0, + /* 1141 - */ 0, + /* 1142 - */ 0, + /* 1143 - */ 0, + /* 1144 - */ 0, + /* 1145 - _V_66_0F_38_2E */ 0x4100, + /* 1146 - */ 0, + /* 1147 - */ 0, + /* 1148 - */ 0, + /* 1149 - */ 0, + /* 114a - */ 0, + /* 114b - */ 0, + /* 114c - */ 0, + /* 114d - */ 0, + /* 114e - */ 0, + /* 114f - */ 0, + /* 1150 - */ 0, + /* 1151 - _V_66_0F_38_2F */ 0x4101, + /* 1152 - */ 0, + /* 1153 - */ 0, + /* 1154 - */ 0, + /* 1155 - */ 0, + /* 1156 - */ 0, + /* 1157 - */ 0, + /* 1158 - */ 0, + /* 1159 - _66_0F_38_30 */ 0x24a6, + /* 115a - */ 0, + /* 115b - */ 0, + /* 115c - */ 0, + /* 115d - _V_66_0F_38_30 */ 0x4102, + /* 115e - */ 0, + /* 115f - */ 0, + /* 1160 - */ 0, + /* 1161 - */ 0, + /* 1162 - */ 0, + /* 1163 - */ 0, + /* 1164 - */ 0, + /* 1165 - _66_0F_38_31 */ 0x24a7, + /* 1166 - */ 0, + /* 1167 - */ 0, + /* 1168 - */ 0, + /* 1169 - _V_66_0F_38_31 */ 0x4103, + /* 116a - */ 0, + /* 116b - */ 0, + /* 116c - */ 0, + /* 116d - */ 0, + /* 116e - */ 0, + /* 116f - */ 0, + /* 1170 - */ 0, + /* 1171 - _66_0F_38_32 */ 0x24a8, + /* 1172 - */ 0, + /* 1173 - */ 0, + /* 1174 - */ 0, + /* 1175 - _V_66_0F_38_32 */ 0x4104, + /* 1176 - */ 0, + /* 1177 - */ 0, + /* 1178 - */ 0, + /* 1179 - */ 0, + /* 117a - */ 0, + /* 117b - */ 0, + /* 117c - */ 0, + /* 117d - _66_0F_38_33 */ 0x24a9, + /* 117e - */ 0, + /* 117f - */ 0, + /* 1180 - */ 0, + /* 1181 - _V_66_0F_38_33 */ 0x4105, + /* 1182 - */ 0, + /* 1183 - */ 0, + /* 1184 - */ 0, + /* 1185 - */ 0, + /* 1186 - */ 0, + /* 1187 - */ 0, + /* 1188 - */ 0, + /* 1189 - _66_0F_38_34 */ 0x24aa, + /* 118a - */ 0, + /* 118b - */ 0, + /* 118c - */ 0, + /* 118d - _V_66_0F_38_34 */ 0x4106, + /* 118e - */ 0, + /* 118f - */ 0, + /* 1190 - */ 0, + /* 1191 - */ 0, + /* 1192 - */ 0, + /* 1193 - */ 0, + /* 1194 - */ 0, + /* 1195 - _66_0F_38_35 */ 0x24ab, + /* 1196 - */ 0, + /* 1197 - */ 0, + /* 1198 - */ 0, + /* 1199 - _V_66_0F_38_35 */ 0x4107, + /* 119a - */ 0, + /* 119b - */ 0, + /* 119c - */ 0, + /* 119d - */ 0, + /* 119e - */ 0, + /* 119f - */ 0, + /* 11a0 - */ 0, + /* 11a1 - _66_0F_38_37 */ 0x24ac, + /* 11a2 - */ 0, + /* 11a3 - */ 0, + /* 11a4 - */ 0, + /* 11a5 - _V_66_0F_38_37 */ 0x4108, + /* 11a6 - */ 0, + /* 11a7 - */ 0, + /* 11a8 - */ 0, + /* 11a9 - */ 0, + /* 11aa - */ 0, + /* 11ab - */ 0, + /* 11ac - */ 0, + /* 11ad - _66_0F_38_38 */ 0x24ad, + /* 11ae - */ 0, + /* 11af - */ 0, + /* 11b0 - */ 0, + /* 11b1 - _V_66_0F_38_38 */ 0x4109, + /* 11b2 - */ 0, + /* 11b3 - */ 0, + /* 11b4 - */ 0, + /* 11b5 - */ 0, + /* 11b6 - */ 0, + /* 11b7 - */ 0, + /* 11b8 - */ 0, + /* 11b9 - _66_0F_38_39 */ 0x24ae, + /* 11ba - */ 0, + /* 11bb - */ 0, + /* 11bc - */ 0, + /* 11bd - _V_66_0F_38_39 */ 0x410a, + /* 11be - */ 0, + /* 11bf - */ 0, + /* 11c0 - */ 0, + /* 11c1 - */ 0, + /* 11c2 - */ 0, + /* 11c3 - */ 0, + /* 11c4 - */ 0, + /* 11c5 - _66_0F_38_3A */ 0x24af, + /* 11c6 - */ 0, + /* 11c7 - */ 0, + /* 11c8 - */ 0, + /* 11c9 - _V_66_0F_38_3A */ 0x410b, + /* 11ca - */ 0, + /* 11cb - */ 0, + /* 11cc - */ 0, + /* 11cd - */ 0, + /* 11ce - */ 0, + /* 11cf - */ 0, + /* 11d0 - */ 0, + /* 11d1 - _66_0F_38_3B */ 0x24b0, + /* 11d2 - */ 0, + /* 11d3 - */ 0, + /* 11d4 - */ 0, + /* 11d5 - _V_66_0F_38_3B */ 0x410c, + /* 11d6 - */ 0, + /* 11d7 - */ 0, + /* 11d8 - */ 0, + /* 11d9 - */ 0, + /* 11da - */ 0, + /* 11db - */ 0, + /* 11dc - */ 0, + /* 11dd - _66_0F_38_3C */ 0x24b1, + /* 11de - */ 0, + /* 11df - */ 0, + /* 11e0 - */ 0, + /* 11e1 - _V_66_0F_38_3C */ 0x410d, + /* 11e2 - */ 0, + /* 11e3 - */ 0, + /* 11e4 - */ 0, + /* 11e5 - */ 0, + /* 11e6 - */ 0, + /* 11e7 - */ 0, + /* 11e8 - */ 0, + /* 11e9 - _66_0F_38_3D */ 0x24b2, + /* 11ea - */ 0, + /* 11eb - */ 0, + /* 11ec - */ 0, + /* 11ed - _V_66_0F_38_3D */ 0x410e, + /* 11ee - */ 0, + /* 11ef - */ 0, + /* 11f0 - */ 0, + /* 11f1 - */ 0, + /* 11f2 - */ 0, + /* 11f3 - */ 0, + /* 11f4 - */ 0, + /* 11f5 - _66_0F_38_3E */ 0x24b3, + /* 11f6 - */ 0, + /* 11f7 - */ 0, + /* 11f8 - */ 0, + /* 11f9 - _V_66_0F_38_3E */ 0x410f, + /* 11fa - */ 0, + /* 11fb - */ 0, + /* 11fc - */ 0, + /* 11fd - */ 0, + /* 11fe - */ 0, + /* 11ff - */ 0, + /* 1200 - */ 0, + /* 1201 - _66_0F_38_3F */ 0x24b4, + /* 1202 - */ 0, + /* 1203 - */ 0, + /* 1204 - */ 0, + /* 1205 - _V_66_0F_38_3F */ 0x4110, + /* 1206 - */ 0, + /* 1207 - */ 0, + /* 1208 - */ 0, + /* 1209 - */ 0, + /* 120a - */ 0, + /* 120b - */ 0, + /* 120c - */ 0, + /* 120d - _66_0F_38_40 */ 0x24b5, + /* 120e - */ 0, + /* 120f - */ 0, + /* 1210 - */ 0, + /* 1211 - _V_66_0F_38_40 */ 0x4111, + /* 1212 - */ 0, + /* 1213 - */ 0, + /* 1214 - */ 0, + /* 1215 - */ 0, + /* 1216 - */ 0, + /* 1217 - */ 0, + /* 1218 - */ 0, + /* 1219 - _66_0F_38_41 */ 0x24b6, + /* 121a - */ 0, + /* 121b - */ 0, + /* 121c - */ 0, + /* 121d - _V_66_0F_38_41 */ 0x4112, + /* 121e - */ 0, + /* 121f - */ 0, + /* 1220 - */ 0, + /* 1221 - */ 0, + /* 1222 - */ 0, + /* 1223 - */ 0, + /* 1224 - */ 0, + /* 1225 - _66_0F_38_80 */ 0x24b7, + /* 1226 - */ 0, + /* 1227 - */ 0, + /* 1228 - */ 0, + /* 1229 - */ 0, + /* 122a - */ 0, + /* 122b - */ 0, + /* 122c - */ 0, + /* 122d - */ 0, + /* 122e - */ 0, + /* 122f - */ 0, + /* 1230 - */ 0, + /* 1231 - _66_0F_38_81 */ 0x24b8, + /* 1232 - */ 0, + /* 1233 - */ 0, + /* 1234 - */ 0, + /* 1235 - */ 0, + /* 1236 - */ 0, + /* 1237 - */ 0, + /* 1238 - */ 0, + /* 1239 - */ 0, + /* 123a - */ 0, + /* 123b - */ 0, + /* 123c - */ 0, + /* 123d - _66_0F_38_82 */ 0x24b9, + /* 123e - */ 0, + /* 123f - */ 0, + /* 1240 - */ 0, + /* 1241 - */ 0, + /* 1242 - */ 0, + /* 1243 - */ 0, + /* 1244 - */ 0, + /* 1245 - */ 0, + /* 1246 - */ 0, + /* 1247 - */ 0, + /* 1248 - */ 0, + /* 1249 - */ 0, + /* 124a - */ 0, + /* 124b - */ 0, + /* 124c - */ 0, + /* 124d - _V_66_0F_38_96 */ 0x4113, + /* 124e - */ 0, + /* 124f - */ 0, + /* 1250 - */ 0, + /* 1251 - */ 0, + /* 1252 - */ 0, + /* 1253 - */ 0, + /* 1254 - */ 0, + /* 1255 - */ 0, + /* 1256 - */ 0, + /* 1257 - */ 0, + /* 1258 - */ 0, + /* 1259 - _V_66_0F_38_97 */ 0x4114, + /* 125a - */ 0, + /* 125b - */ 0, + /* 125c - */ 0, + /* 125d - */ 0, + /* 125e - */ 0, + /* 125f - */ 0, + /* 1260 - */ 0, + /* 1261 - */ 0, + /* 1262 - */ 0, + /* 1263 - */ 0, + /* 1264 - */ 0, + /* 1265 - _V_66_0F_38_98 */ 0x4115, + /* 1266 - */ 0, + /* 1267 - */ 0, + /* 1268 - */ 0, + /* 1269 - */ 0, + /* 126a - */ 0, + /* 126b - */ 0, + /* 126c - */ 0, + /* 126d - */ 0, + /* 126e - */ 0, + /* 126f - */ 0, + /* 1270 - */ 0, + /* 1271 - _V_66_0F_38_99 */ 0x4116, + /* 1272 - */ 0, + /* 1273 - */ 0, + /* 1274 - */ 0, + /* 1275 - */ 0, + /* 1276 - */ 0, + /* 1277 - */ 0, + /* 1278 - */ 0, + /* 1279 - */ 0, + /* 127a - */ 0, + /* 127b - */ 0, + /* 127c - */ 0, + /* 127d - _V_66_0F_38_9A */ 0x4117, + /* 127e - */ 0, + /* 127f - */ 0, + /* 1280 - */ 0, + /* 1281 - */ 0, + /* 1282 - */ 0, + /* 1283 - */ 0, + /* 1284 - */ 0, + /* 1285 - */ 0, + /* 1286 - */ 0, + /* 1287 - */ 0, + /* 1288 - */ 0, + /* 1289 - _V_66_0F_38_9B */ 0x4118, + /* 128a - */ 0, + /* 128b - */ 0, + /* 128c - */ 0, + /* 128d - */ 0, + /* 128e - */ 0, + /* 128f - */ 0, + /* 1290 - */ 0, + /* 1291 - */ 0, + /* 1292 - */ 0, + /* 1293 - */ 0, + /* 1294 - */ 0, + /* 1295 - _V_66_0F_38_9C */ 0x4119, + /* 1296 - */ 0, + /* 1297 - */ 0, + /* 1298 - */ 0, + /* 1299 - */ 0, + /* 129a - */ 0, + /* 129b - */ 0, + /* 129c - */ 0, + /* 129d - */ 0, + /* 129e - */ 0, + /* 129f - */ 0, + /* 12a0 - */ 0, + /* 12a1 - _V_66_0F_38_9D */ 0x411a, + /* 12a2 - */ 0, + /* 12a3 - */ 0, + /* 12a4 - */ 0, + /* 12a5 - */ 0, + /* 12a6 - */ 0, + /* 12a7 - */ 0, + /* 12a8 - */ 0, + /* 12a9 - */ 0, + /* 12aa - */ 0, + /* 12ab - */ 0, + /* 12ac - */ 0, + /* 12ad - _V_66_0F_38_9E */ 0x411b, + /* 12ae - */ 0, + /* 12af - */ 0, + /* 12b0 - */ 0, + /* 12b1 - */ 0, + /* 12b2 - */ 0, + /* 12b3 - */ 0, + /* 12b4 - */ 0, + /* 12b5 - */ 0, + /* 12b6 - */ 0, + /* 12b7 - */ 0, + /* 12b8 - */ 0, + /* 12b9 - _V_66_0F_38_9F */ 0x411c, + /* 12ba - */ 0, + /* 12bb - */ 0, + /* 12bc - */ 0, + /* 12bd - */ 0, + /* 12be - */ 0, + /* 12bf - */ 0, + /* 12c0 - */ 0, + /* 12c1 - */ 0, + /* 12c2 - */ 0, + /* 12c3 - */ 0, + /* 12c4 - */ 0, + /* 12c5 - _V_66_0F_38_A6 */ 0x411d, + /* 12c6 - */ 0, + /* 12c7 - */ 0, + /* 12c8 - */ 0, + /* 12c9 - */ 0, + /* 12ca - */ 0, + /* 12cb - */ 0, + /* 12cc - */ 0, + /* 12cd - */ 0, + /* 12ce - */ 0, + /* 12cf - */ 0, + /* 12d0 - */ 0, + /* 12d1 - _V_66_0F_38_A7 */ 0x411e, + /* 12d2 - */ 0, + /* 12d3 - */ 0, + /* 12d4 - */ 0, + /* 12d5 - */ 0, + /* 12d6 - */ 0, + /* 12d7 - */ 0, + /* 12d8 - */ 0, + /* 12d9 - */ 0, + /* 12da - */ 0, + /* 12db - */ 0, + /* 12dc - */ 0, + /* 12dd - _V_66_0F_38_A8 */ 0x411f, + /* 12de - */ 0, + /* 12df - */ 0, + /* 12e0 - */ 0, + /* 12e1 - */ 0, + /* 12e2 - */ 0, + /* 12e3 - */ 0, + /* 12e4 - */ 0, + /* 12e5 - */ 0, + /* 12e6 - */ 0, + /* 12e7 - */ 0, + /* 12e8 - */ 0, + /* 12e9 - _V_66_0F_38_A9 */ 0x4120, + /* 12ea - */ 0, + /* 12eb - */ 0, + /* 12ec - */ 0, + /* 12ed - */ 0, + /* 12ee - */ 0, + /* 12ef - */ 0, + /* 12f0 - */ 0, + /* 12f1 - */ 0, + /* 12f2 - */ 0, + /* 12f3 - */ 0, + /* 12f4 - */ 0, + /* 12f5 - _V_66_0F_38_AA */ 0x4121, + /* 12f6 - */ 0, + /* 12f7 - */ 0, + /* 12f8 - */ 0, + /* 12f9 - */ 0, + /* 12fa - */ 0, + /* 12fb - */ 0, + /* 12fc - */ 0, + /* 12fd - */ 0, + /* 12fe - */ 0, + /* 12ff - */ 0, + /* 1300 - */ 0, + /* 1301 - _V_66_0F_38_AB */ 0x4122, + /* 1302 - */ 0, + /* 1303 - */ 0, + /* 1304 - */ 0, + /* 1305 - */ 0, + /* 1306 - */ 0, + /* 1307 - */ 0, + /* 1308 - */ 0, + /* 1309 - */ 0, + /* 130a - */ 0, + /* 130b - */ 0, + /* 130c - */ 0, + /* 130d - _V_66_0F_38_AC */ 0x4123, + /* 130e - */ 0, + /* 130f - */ 0, + /* 1310 - */ 0, + /* 1311 - */ 0, + /* 1312 - */ 0, + /* 1313 - */ 0, + /* 1314 - */ 0, + /* 1315 - */ 0, + /* 1316 - */ 0, + /* 1317 - */ 0, + /* 1318 - */ 0, + /* 1319 - _V_66_0F_38_AD */ 0x4124, + /* 131a - */ 0, + /* 131b - */ 0, + /* 131c - */ 0, + /* 131d - */ 0, + /* 131e - */ 0, + /* 131f - */ 0, + /* 1320 - */ 0, + /* 1321 - */ 0, + /* 1322 - */ 0, + /* 1323 - */ 0, + /* 1324 - */ 0, + /* 1325 - _V_66_0F_38_AE */ 0x4125, + /* 1326 - */ 0, + /* 1327 - */ 0, + /* 1328 - */ 0, + /* 1329 - */ 0, + /* 132a - */ 0, + /* 132b - */ 0, + /* 132c - */ 0, + /* 132d - */ 0, + /* 132e - */ 0, + /* 132f - */ 0, + /* 1330 - */ 0, + /* 1331 - _V_66_0F_38_AF */ 0x4126, + /* 1332 - */ 0, + /* 1333 - */ 0, + /* 1334 - */ 0, + /* 1335 - */ 0, + /* 1336 - */ 0, + /* 1337 - */ 0, + /* 1338 - */ 0, + /* 1339 - */ 0, + /* 133a - */ 0, + /* 133b - */ 0, + /* 133c - */ 0, + /* 133d - _V_66_0F_38_B6 */ 0x4127, + /* 133e - */ 0, + /* 133f - */ 0, + /* 1340 - */ 0, + /* 1341 - */ 0, + /* 1342 - */ 0, + /* 1343 - */ 0, + /* 1344 - */ 0, + /* 1345 - */ 0, + /* 1346 - */ 0, + /* 1347 - */ 0, + /* 1348 - */ 0, + /* 1349 - _V_66_0F_38_B7 */ 0x4128, + /* 134a - */ 0, + /* 134b - */ 0, + /* 134c - */ 0, + /* 134d - */ 0, + /* 134e - */ 0, + /* 134f - */ 0, + /* 1350 - */ 0, + /* 1351 - */ 0, + /* 1352 - */ 0, + /* 1353 - */ 0, + /* 1354 - */ 0, + /* 1355 - _V_66_0F_38_B8 */ 0x4129, + /* 1356 - */ 0, + /* 1357 - */ 0, + /* 1358 - */ 0, + /* 1359 - */ 0, + /* 135a - */ 0, + /* 135b - */ 0, + /* 135c - */ 0, + /* 135d - */ 0, + /* 135e - */ 0, + /* 135f - */ 0, + /* 1360 - */ 0, + /* 1361 - _V_66_0F_38_B9 */ 0x412a, + /* 1362 - */ 0, + /* 1363 - */ 0, + /* 1364 - */ 0, + /* 1365 - */ 0, + /* 1366 - */ 0, + /* 1367 - */ 0, + /* 1368 - */ 0, + /* 1369 - */ 0, + /* 136a - */ 0, + /* 136b - */ 0, + /* 136c - */ 0, + /* 136d - _V_66_0F_38_BA */ 0x412b, + /* 136e - */ 0, + /* 136f - */ 0, + /* 1370 - */ 0, + /* 1371 - */ 0, + /* 1372 - */ 0, + /* 1373 - */ 0, + /* 1374 - */ 0, + /* 1375 - */ 0, + /* 1376 - */ 0, + /* 1377 - */ 0, + /* 1378 - */ 0, + /* 1379 - _V_66_0F_38_BB */ 0x412c, + /* 137a - */ 0, + /* 137b - */ 0, + /* 137c - */ 0, + /* 137d - */ 0, + /* 137e - */ 0, + /* 137f - */ 0, + /* 1380 - */ 0, + /* 1381 - */ 0, + /* 1382 - */ 0, + /* 1383 - */ 0, + /* 1384 - */ 0, + /* 1385 - _V_66_0F_38_BC */ 0x412d, + /* 1386 - */ 0, + /* 1387 - */ 0, + /* 1388 - */ 0, + /* 1389 - */ 0, + /* 138a - */ 0, + /* 138b - */ 0, + /* 138c - */ 0, + /* 138d - */ 0, + /* 138e - */ 0, + /* 138f - */ 0, + /* 1390 - */ 0, + /* 1391 - _V_66_0F_38_BD */ 0x412e, + /* 1392 - */ 0, + /* 1393 - */ 0, + /* 1394 - */ 0, + /* 1395 - */ 0, + /* 1396 - */ 0, + /* 1397 - */ 0, + /* 1398 - */ 0, + /* 1399 - */ 0, + /* 139a - */ 0, + /* 139b - */ 0, + /* 139c - */ 0, + /* 139d - _V_66_0F_38_BE */ 0x412f, + /* 139e - */ 0, + /* 139f - */ 0, + /* 13a0 - */ 0, + /* 13a1 - */ 0, + /* 13a2 - */ 0, + /* 13a3 - */ 0, + /* 13a4 - */ 0, + /* 13a5 - */ 0, + /* 13a6 - */ 0, + /* 13a7 - */ 0, + /* 13a8 - */ 0, + /* 13a9 - _V_66_0F_38_BF */ 0x4130, + /* 13aa - */ 0, + /* 13ab - */ 0, + /* 13ac - */ 0, + /* 13ad - */ 0, + /* 13ae - */ 0, + /* 13af - */ 0, + /* 13b0 - */ 0, + /* 13b1 - _66_0F_38_DB */ 0x24ba, + /* 13b2 - */ 0, + /* 13b3 - */ 0, + /* 13b4 - */ 0, + /* 13b5 - _V_66_0F_38_DB */ 0x4131, + /* 13b6 - */ 0, + /* 13b7 - */ 0, + /* 13b8 - */ 0, + /* 13b9 - */ 0, + /* 13ba - */ 0, + /* 13bb - */ 0, + /* 13bc - */ 0, + /* 13bd - _66_0F_38_DC */ 0x24bb, + /* 13be - */ 0, + /* 13bf - */ 0, + /* 13c0 - */ 0, + /* 13c1 - _V_66_0F_38_DC */ 0x4132, + /* 13c2 - */ 0, + /* 13c3 - */ 0, + /* 13c4 - */ 0, + /* 13c5 - */ 0, + /* 13c6 - */ 0, + /* 13c7 - */ 0, + /* 13c8 - */ 0, + /* 13c9 - _66_0F_38_DD */ 0x24bc, + /* 13ca - */ 0, + /* 13cb - */ 0, + /* 13cc - */ 0, + /* 13cd - _V_66_0F_38_DD */ 0x4133, + /* 13ce - */ 0, + /* 13cf - */ 0, + /* 13d0 - */ 0, + /* 13d1 - */ 0, + /* 13d2 - */ 0, + /* 13d3 - */ 0, + /* 13d4 - */ 0, + /* 13d5 - _66_0F_38_DE */ 0x24bd, + /* 13d6 - */ 0, + /* 13d7 - */ 0, + /* 13d8 - */ 0, + /* 13d9 - _V_66_0F_38_DE */ 0x4134, + /* 13da - */ 0, + /* 13db - */ 0, + /* 13dc - */ 0, + /* 13dd - */ 0, + /* 13de - */ 0, + /* 13df - */ 0, + /* 13e0 - */ 0, + /* 13e1 - _66_0F_38_DF */ 0x24be, + /* 13e2 - */ 0, + /* 13e3 - */ 0, + /* 13e4 - */ 0, + /* 13e5 - _V_66_0F_38_DF */ 0x4135, + /* 13e6 - */ 0, + /* 13e7 - */ 0, + /* 13e8 - */ 0, + /* 13e9 - */ 0, + /* 13ea - */ 0, + /* 13eb - */ 0, + /* 13ec - _0F_38_F0 */ 0x24bf, + /* 13ed - */ 0, + /* 13ee - */ 0, + /* 13ef - _F2_0F_38_F0 */ 0x24c0, + /* 13f0 - */ 0, + /* 13f1 - */ 0, + /* 13f2 - */ 0, + /* 13f3 - */ 0, + /* 13f4 - */ 0, + /* 13f5 - */ 0, + /* 13f6 - */ 0, + /* 13f7 - */ 0, + /* 13f8 - _0F_38_F1 */ 0x24c1, + /* 13f9 - */ 0, + /* 13fa - */ 0, + /* 13fb - _F2_0F_38_F1 */ 0x24c2, + /* 13fc - */ 0, + /* 13fd - */ 0, + /* 13fe - */ 0, + /* 13ff - */ 0, + /* 1400 - */ 0, + /* 1401 - */ 0, + /* 1402 - */ 0, + /* 1403 - */ 0, + /* 1404 - */ 0, + /* 1405 - */ 0, + /* 1406 - */ 0, + /* 1407 - */ 0, + /* 1408 - */ 0, + /* 1409 - _V_66_0F_3A_04 */ 0x4136, + /* 140a - */ 0, + /* 140b - */ 0, + /* 140c - */ 0, + /* 140d - */ 0, + /* 140e - */ 0, + /* 140f - */ 0, + /* 1410 - */ 0, + /* 1411 - */ 0, + /* 1412 - */ 0, + /* 1413 - */ 0, + /* 1414 - */ 0, + /* 1415 - _V_66_0F_3A_05 */ 0x4137, + /* 1416 - */ 0, + /* 1417 - */ 0, + /* 1418 - */ 0, + /* 1419 - */ 0, + /* 141a - */ 0, + /* 141b - */ 0, + /* 141c - */ 0, + /* 141d - */ 0, + /* 141e - */ 0, + /* 141f - */ 0, + /* 1420 - */ 0, + /* 1421 - _V_66_0F_3A_06 */ 0x4138, + /* 1422 - */ 0, + /* 1423 - */ 0, + /* 1424 - */ 0, + /* 1425 - */ 0, + /* 1426 - */ 0, + /* 1427 - */ 0, + /* 1428 - */ 0, + /* 1429 - _66_0F_3A_08 */ 0x4139, + /* 142a - */ 0, + /* 142b - */ 0, + /* 142c - */ 0, + /* 142d - _V_66_0F_3A_08 */ 0x413a, + /* 142e - */ 0, + /* 142f - */ 0, + /* 1430 - */ 0, + /* 1431 - */ 0, + /* 1432 - */ 0, + /* 1433 - */ 0, + /* 1434 - */ 0, + /* 1435 - _66_0F_3A_09 */ 0x413b, + /* 1436 - */ 0, + /* 1437 - */ 0, + /* 1438 - */ 0, + /* 1439 - _V_66_0F_3A_09 */ 0x413c, + /* 143a - */ 0, + /* 143b - */ 0, + /* 143c - */ 0, + /* 143d - */ 0, + /* 143e - */ 0, + /* 143f - */ 0, + /* 1440 - */ 0, + /* 1441 - _66_0F_3A_0A */ 0x413d, + /* 1442 - */ 0, + /* 1443 - */ 0, + /* 1444 - */ 0, + /* 1445 - _V_66_0F_3A_0A */ 0x413e, + /* 1446 - */ 0, + /* 1447 - */ 0, + /* 1448 - */ 0, + /* 1449 - */ 0, + /* 144a - */ 0, + /* 144b - */ 0, + /* 144c - */ 0, + /* 144d - _66_0F_3A_0B */ 0x413f, + /* 144e - */ 0, + /* 144f - */ 0, + /* 1450 - */ 0, + /* 1451 - _V_66_0F_3A_0B */ 0x4140, + /* 1452 - */ 0, + /* 1453 - */ 0, + /* 1454 - */ 0, + /* 1455 - */ 0, + /* 1456 - */ 0, + /* 1457 - */ 0, + /* 1458 - */ 0, + /* 1459 - _66_0F_3A_0C */ 0x4141, + /* 145a - */ 0, + /* 145b - */ 0, + /* 145c - */ 0, + /* 145d - _V_66_0F_3A_0C */ 0x4142, + /* 145e - */ 0, + /* 145f - */ 0, + /* 1460 - */ 0, + /* 1461 - */ 0, + /* 1462 - */ 0, + /* 1463 - */ 0, + /* 1464 - */ 0, + /* 1465 - _66_0F_3A_0D */ 0x4143, + /* 1466 - */ 0, + /* 1467 - */ 0, + /* 1468 - */ 0, + /* 1469 - _V_66_0F_3A_0D */ 0x4144, + /* 146a - */ 0, + /* 146b - */ 0, + /* 146c - */ 0, + /* 146d - */ 0, + /* 146e - */ 0, + /* 146f - */ 0, + /* 1470 - */ 0, + /* 1471 - _66_0F_3A_0E */ 0x4145, + /* 1472 - */ 0, + /* 1473 - */ 0, + /* 1474 - */ 0, + /* 1475 - _V_66_0F_3A_0E */ 0x4146, + /* 1476 - */ 0, + /* 1477 - */ 0, + /* 1478 - */ 0, + /* 1479 - */ 0, + /* 147a - */ 0, + /* 147b - */ 0, + /* 147c - _0F_3A_0F */ 0x4147, + /* 147d - _66_0F_3A_0F */ 0x4148, + /* 147e - */ 0, + /* 147f - */ 0, + /* 1480 - */ 0, + /* 1481 - _V_66_0F_3A_0F */ 0x4149, + /* 1482 - */ 0, + /* 1483 - */ 0, + /* 1484 - */ 0, + /* 1485 - */ 0, + /* 1486 - */ 0, + /* 1487 - */ 0, + /* 1488 - */ 0, + /* 1489 - _66_0F_3A_14 */ 0x414a, + /* 148a - */ 0, + /* 148b - */ 0, + /* 148c - */ 0, + /* 148d - _V_66_0F_3A_14 */ 0x414b, + /* 148e - */ 0, + /* 148f - */ 0, + /* 1490 - */ 0, + /* 1491 - */ 0, + /* 1492 - */ 0, + /* 1493 - */ 0, + /* 1494 - */ 0, + /* 1495 - _66_0F_3A_15 */ 0x414c, + /* 1496 - */ 0, + /* 1497 - */ 0, + /* 1498 - */ 0, + /* 1499 - _V_66_0F_3A_15 */ 0x414d, + /* 149a - */ 0, + /* 149b - */ 0, + /* 149c - */ 0, + /* 149d - */ 0, + /* 149e - */ 0, + /* 149f - */ 0, + /* 14a0 - */ 0, + /* 14a1 - _66_0F_3A_16 */ 0x414e, + /* 14a2 - */ 0, + /* 14a3 - */ 0, + /* 14a4 - */ 0, + /* 14a5 - _V_66_0F_3A_16 */ 0x414f, + /* 14a6 - */ 0, + /* 14a7 - */ 0, + /* 14a8 - */ 0, + /* 14a9 - */ 0, + /* 14aa - */ 0, + /* 14ab - */ 0, + /* 14ac - */ 0, + /* 14ad - _66_0F_3A_17 */ 0x4150, + /* 14ae - */ 0, + /* 14af - */ 0, + /* 14b0 - */ 0, + /* 14b1 - _V_66_0F_3A_17 */ 0x4151, + /* 14b2 - */ 0, + /* 14b3 - */ 0, + /* 14b4 - */ 0, + /* 14b5 - */ 0, + /* 14b6 - */ 0, + /* 14b7 - */ 0, + /* 14b8 - */ 0, + /* 14b9 - */ 0, + /* 14ba - */ 0, + /* 14bb - */ 0, + /* 14bc - */ 0, + /* 14bd - _V_66_0F_3A_18 */ 0x4152, + /* 14be - */ 0, + /* 14bf - */ 0, + /* 14c0 - */ 0, + /* 14c1 - */ 0, + /* 14c2 - */ 0, + /* 14c3 - */ 0, + /* 14c4 - */ 0, + /* 14c5 - */ 0, + /* 14c6 - */ 0, + /* 14c7 - */ 0, + /* 14c8 - */ 0, + /* 14c9 - _V_66_0F_3A_19 */ 0x4153, + /* 14ca - */ 0, + /* 14cb - */ 0, + /* 14cc - */ 0, + /* 14cd - */ 0, + /* 14ce - */ 0, + /* 14cf - */ 0, + /* 14d0 - */ 0, + /* 14d1 - _66_0F_3A_20 */ 0x4154, + /* 14d2 - */ 0, + /* 14d3 - */ 0, + /* 14d4 - */ 0, + /* 14d5 - _V_66_0F_3A_20 */ 0x4155, + /* 14d6 - */ 0, + /* 14d7 - */ 0, + /* 14d8 - */ 0, + /* 14d9 - */ 0, + /* 14da - */ 0, + /* 14db - */ 0, + /* 14dc - */ 0, + /* 14dd - _66_0F_3A_21 */ 0x4156, + /* 14de - */ 0, + /* 14df - */ 0, + /* 14e0 - */ 0, + /* 14e1 - _V_66_0F_3A_21 */ 0x4157, + /* 14e2 - */ 0, + /* 14e3 - */ 0, + /* 14e4 - */ 0, + /* 14e5 - */ 0, + /* 14e6 - */ 0, + /* 14e7 - */ 0, + /* 14e8 - */ 0, + /* 14e9 - _66_0F_3A_22 */ 0x4158, + /* 14ea - */ 0, + /* 14eb - */ 0, + /* 14ec - */ 0, + /* 14ed - _V_66_0F_3A_22 */ 0x4159, + /* 14ee - */ 0, + /* 14ef - */ 0, + /* 14f0 - */ 0, + /* 14f1 - */ 0, + /* 14f2 - */ 0, + /* 14f3 - */ 0, + /* 14f4 - */ 0, + /* 14f5 - _66_0F_3A_40 */ 0x415a, + /* 14f6 - */ 0, + /* 14f7 - */ 0, + /* 14f8 - */ 0, + /* 14f9 - _V_66_0F_3A_40 */ 0x415b, + /* 14fa - */ 0, + /* 14fb - */ 0, + /* 14fc - */ 0, + /* 14fd - */ 0, + /* 14fe - */ 0, + /* 14ff - */ 0, + /* 1500 - */ 0, + /* 1501 - _66_0F_3A_41 */ 0x415c, + /* 1502 - */ 0, + /* 1503 - */ 0, + /* 1504 - */ 0, + /* 1505 - _V_66_0F_3A_41 */ 0x415d, + /* 1506 - */ 0, + /* 1507 - */ 0, + /* 1508 - */ 0, + /* 1509 - */ 0, + /* 150a - */ 0, + /* 150b - */ 0, + /* 150c - */ 0, + /* 150d - _66_0F_3A_42 */ 0x415e, + /* 150e - */ 0, + /* 150f - */ 0, + /* 1510 - */ 0, + /* 1511 - _V_66_0F_3A_42 */ 0x415f, + /* 1512 - */ 0, + /* 1513 - */ 0, + /* 1514 - */ 0, + /* 1515 - */ 0, + /* 1516 - */ 0, + /* 1517 - */ 0, + /* 1518 - */ 0, + /* 1519 - _66_0F_3A_44 */ 0x4160, + /* 151a - */ 0, + /* 151b - */ 0, + /* 151c - */ 0, + /* 151d - _V_66_0F_3A_44 */ 0x4161, + /* 151e - */ 0, + /* 151f - */ 0, + /* 1520 - */ 0, + /* 1521 - */ 0, + /* 1522 - */ 0, + /* 1523 - */ 0, + /* 1524 - */ 0, + /* 1525 - */ 0, + /* 1526 - */ 0, + /* 1527 - */ 0, + /* 1528 - */ 0, + /* 1529 - _V_66_0F_3A_4A */ 0x4162, + /* 152a - */ 0, + /* 152b - */ 0, + /* 152c - */ 0, + /* 152d - */ 0, + /* 152e - */ 0, + /* 152f - */ 0, + /* 1530 - */ 0, + /* 1531 - */ 0, + /* 1532 - */ 0, + /* 1533 - */ 0, + /* 1534 - */ 0, + /* 1535 - _V_66_0F_3A_4B */ 0x4163, + /* 1536 - */ 0, + /* 1537 - */ 0, + /* 1538 - */ 0, + /* 1539 - */ 0, + /* 153a - */ 0, + /* 153b - */ 0, + /* 153c - */ 0, + /* 153d - */ 0, + /* 153e - */ 0, + /* 153f - */ 0, + /* 1540 - */ 0, + /* 1541 - _V_66_0F_3A_4C */ 0x4164, + /* 1542 - */ 0, + /* 1543 - */ 0, + /* 1544 - */ 0, + /* 1545 - */ 0, + /* 1546 - */ 0, + /* 1547 - */ 0, + /* 1548 - */ 0, + /* 1549 - _66_0F_3A_60 */ 0x4165, + /* 154a - */ 0, + /* 154b - */ 0, + /* 154c - */ 0, + /* 154d - _V_66_0F_3A_60 */ 0x4166, + /* 154e - */ 0, + /* 154f - */ 0, + /* 1550 - */ 0, + /* 1551 - */ 0, + /* 1552 - */ 0, + /* 1553 - */ 0, + /* 1554 - */ 0, + /* 1555 - _66_0F_3A_61 */ 0x4167, + /* 1556 - */ 0, + /* 1557 - */ 0, + /* 1558 - */ 0, + /* 1559 - _V_66_0F_3A_61 */ 0x4168, + /* 155a - */ 0, + /* 155b - */ 0, + /* 155c - */ 0, + /* 155d - */ 0, + /* 155e - */ 0, + /* 155f - */ 0, + /* 1560 - */ 0, + /* 1561 - _66_0F_3A_62 */ 0x4169, + /* 1562 - */ 0, + /* 1563 - */ 0, + /* 1564 - */ 0, + /* 1565 - _V_66_0F_3A_62 */ 0x416a, + /* 1566 - */ 0, + /* 1567 - */ 0, + /* 1568 - */ 0, + /* 1569 - */ 0, + /* 156a - */ 0, + /* 156b - */ 0, + /* 156c - */ 0, + /* 156d - _66_0F_3A_63 */ 0x416b, + /* 156e - */ 0, + /* 156f - */ 0, + /* 1570 - */ 0, + /* 1571 - _V_66_0F_3A_63 */ 0x416c, + /* 1572 - */ 0, + /* 1573 - */ 0, + /* 1574 - */ 0, + /* 1575 - */ 0, + /* 1576 - */ 0, + /* 1577 - */ 0, + /* 1578 - */ 0, + /* 1579 - _66_0F_3A_DF */ 0x416d, + /* 157a - */ 0, + /* 157b - */ 0, + /* 157c - */ 0, + /* 157d - _V_66_0F_3A_DF */ 0x416e, + /* 157e - */ 0, + /* 157f - */ 0, + /* 1580 - */ 0, + /* 1581 - */ 0, + /* 1582 - */ 0, + /* 1583 - */ 0, + /* 1584 - _0F_71_02 */ 0x24c3, + /* 1585 - _66_0F_71_02 */ 0x24c4, + /* 1586 - */ 0, + /* 1587 - */ 0, + /* 1588 - */ 0, + /* 1589 - _V_66_0F_71_02 */ 0x416f, + /* 158a - */ 0, + /* 158b - */ 0, + /* 158c - */ 0, + /* 158d - */ 0, + /* 158e - */ 0, + /* 158f - */ 0, + /* 1590 - _0F_71_04 */ 0x24c5, + /* 1591 - _66_0F_71_04 */ 0x24c6, + /* 1592 - */ 0, + /* 1593 - */ 0, + /* 1594 - */ 0, + /* 1595 - _V_66_0F_71_04 */ 0x4170, + /* 1596 - */ 0, + /* 1597 - */ 0, + /* 1598 - */ 0, + /* 1599 - */ 0, + /* 159a - */ 0, + /* 159b - */ 0, + /* 159c - _0F_71_06 */ 0x24c7, + /* 159d - _66_0F_71_06 */ 0x24c8, + /* 159e - */ 0, + /* 159f - */ 0, + /* 15a0 - */ 0, + /* 15a1 - _V_66_0F_71_06 */ 0x4171, + /* 15a2 - */ 0, + /* 15a3 - */ 0, + /* 15a4 - */ 0, + /* 15a5 - */ 0, + /* 15a6 - */ 0, + /* 15a7 - */ 0, + /* 15a8 - _0F_72_02 */ 0x24c9, + /* 15a9 - _66_0F_72_02 */ 0x24ca, + /* 15aa - */ 0, + /* 15ab - */ 0, + /* 15ac - */ 0, + /* 15ad - _V_66_0F_72_02 */ 0x4172, + /* 15ae - */ 0, + /* 15af - */ 0, + /* 15b0 - */ 0, + /* 15b1 - */ 0, + /* 15b2 - */ 0, + /* 15b3 - */ 0, + /* 15b4 - _0F_72_04 */ 0x24cb, + /* 15b5 - _66_0F_72_04 */ 0x24cc, + /* 15b6 - */ 0, + /* 15b7 - */ 0, + /* 15b8 - */ 0, + /* 15b9 - _V_66_0F_72_04 */ 0x4173, + /* 15ba - */ 0, + /* 15bb - */ 0, + /* 15bc - */ 0, + /* 15bd - */ 0, + /* 15be - */ 0, + /* 15bf - */ 0, + /* 15c0 - _0F_72_06 */ 0x24cd, + /* 15c1 - _66_0F_72_06 */ 0x24ce, + /* 15c2 - */ 0, + /* 15c3 - */ 0, + /* 15c4 - */ 0, + /* 15c5 - _V_66_0F_72_06 */ 0x4174, + /* 15c6 - */ 0, + /* 15c7 - */ 0, + /* 15c8 - */ 0, + /* 15c9 - */ 0, + /* 15ca - */ 0, + /* 15cb - */ 0, + /* 15cc - _0F_73_02 */ 0x24cf, + /* 15cd - _66_0F_73_02 */ 0x24d0, + /* 15ce - */ 0, + /* 15cf - */ 0, + /* 15d0 - */ 0, + /* 15d1 - _V_66_0F_73_02 */ 0x4175, + /* 15d2 - */ 0, + /* 15d3 - */ 0, + /* 15d4 - */ 0, + /* 15d5 - */ 0, + /* 15d6 - */ 0, + /* 15d7 - */ 0, + /* 15d8 - */ 0, + /* 15d9 - _66_0F_73_03 */ 0x24d1, + /* 15da - */ 0, + /* 15db - */ 0, + /* 15dc - */ 0, + /* 15dd - _V_66_0F_73_03 */ 0x4176, + /* 15de - */ 0, + /* 15df - */ 0, + /* 15e0 - */ 0, + /* 15e1 - */ 0, + /* 15e2 - */ 0, + /* 15e3 - */ 0, + /* 15e4 - _0F_73_06 */ 0x24d2, + /* 15e5 - _66_0F_73_06 */ 0x24d3, + /* 15e6 - */ 0, + /* 15e7 - */ 0, + /* 15e8 - */ 0, + /* 15e9 - _V_66_0F_73_06 */ 0x4177, + /* 15ea - */ 0, + /* 15eb - */ 0, + /* 15ec - */ 0, + /* 15ed - */ 0, + /* 15ee - */ 0, + /* 15ef - */ 0, + /* 15f0 - */ 0, + /* 15f1 - _66_0F_73_07 */ 0x24d4, + /* 15f2 - */ 0, + /* 15f3 - */ 0, + /* 15f4 - */ 0, + /* 15f5 - _V_66_0F_73_07 */ 0x4178, + /* 15f6 - */ 0, + /* 15f7 - */ 0, + /* 15f8 - */ 0, + /* 15f9 - */ 0, + /* 15fa - */ 0, + /* 15fb - */ 0, + /* 15fc - _0F_AE_00 */ 0x4179, + /* 15fd - */ 0, + /* 15fe - _F3_0F_AE_00 */ 0x24d5, + /* 15ff - */ 0, + /* 1600 - */ 0, + /* 1601 - */ 0, + /* 1602 - */ 0, + /* 1603 - */ 0, + /* 1604 - */ 0, + /* 1605 - */ 0, + /* 1606 - */ 0, + /* 1607 - */ 0, + /* 1608 - _0F_AE_01 */ 0x417a, + /* 1609 - */ 0, + /* 160a - _F3_0F_AE_01 */ 0x24d6, + /* 160b - */ 0, + /* 160c - */ 0, + /* 160d - */ 0, + /* 160e - */ 0, + /* 160f - */ 0, + /* 1610 - */ 0, + /* 1611 - */ 0, + /* 1612 - */ 0, + /* 1613 - */ 0, + /* 1614 - _0F_AE_02 */ 0x24d7, + /* 1615 - */ 0, + /* 1616 - _F3_0F_AE_02 */ 0x24d8, + /* 1617 - */ 0, + /* 1618 - _V_0F_AE_02 */ 0x417b, + /* 1619 - */ 0, + /* 161a - */ 0, + /* 161b - */ 0, + /* 161c - */ 0, + /* 161d - */ 0, + /* 161e - */ 0, + /* 161f - */ 0, + /* 1620 - _0F_AE_03 */ 0x24d9, + /* 1621 - */ 0, + /* 1622 - _F3_0F_AE_03 */ 0x24da, + /* 1623 - */ 0, + /* 1624 - _V_0F_AE_03 */ 0x417c, + /* 1625 - */ 0, + /* 1626 - */ 0, + /* 1627 - */ 0, + /* 1628 - */ 0, + /* 1629 - */ 0, + /* 162a - */ 0, + /* 162b - */ 0, + /* 162c - _0F_C7_06 */ 0x24db, + /* 162d - _66_0F_C7_06 */ 0x24dc, + /* 162e - _F3_0F_C7_06 */ 0x24dd, + /* 162f - */ 0, + /* 1630 - */ 0, + /* 1631 - */ 0, + /* 1632 - */ 0, + /* 1633 - */ 0, + /* 1634 - */ 0, + /* 1635 - */ 0, + /* 1636 - */ 0, + /* 1637 - */ 0 +}; + +_InstSharedInfo InstSharedInfoTable[470] = { + { 0, 9, 15, 8, 245, 0, 0 }, + { 0, 11, 17, 8, 245, 0, 0 }, + { 0, 15, 9, 8, 245, 0, 0 }, + { 0, 17, 11, 8, 245, 0, 0 }, + { 1, 1, 33, 8, 245, 0, 0 }, + { 1, 3, 35, 8, 245, 0, 0 }, + { 2, 0, 32, 8, 0, 0, 0 }, + { 3, 0, 32, 8, 0, 0, 0 }, + { 0, 9, 15, 8, 196, 16, 0 }, + { 0, 11, 17, 8, 196, 16, 0 }, + { 0, 15, 9, 8, 196, 16, 0 }, + { 0, 17, 11, 8, 196, 16, 0 }, + { 1, 1, 33, 8, 196, 16, 0 }, + { 1, 3, 35, 8, 196, 16, 0 }, + { 4, 0, 32, 8, 0, 0, 0 }, + { 0, 9, 15, 8, 245, 1, 0 }, + { 0, 11, 17, 8, 245, 1, 0 }, + { 0, 15, 9, 8, 245, 1, 0 }, + { 0, 17, 11, 8, 245, 1, 0 }, + { 1, 1, 33, 8, 245, 1, 0 }, + { 1, 3, 35, 8, 245, 1, 0 }, + { 5, 0, 32, 8, 0, 0, 0 }, + { 6, 0, 32, 8, 0, 0, 0 }, + { 7, 0, 32, 8, 0, 0, 0 }, + { 8, 0, 32, 8, 0, 0, 0 }, + { 0, 9, 15, 8, 229, 0, 16 }, + { 0, 11, 17, 8, 229, 0, 16 }, + { 0, 15, 9, 8, 229, 0, 16 }, + { 0, 17, 11, 8, 229, 0, 16 }, + { 1, 1, 33, 8, 229, 0, 16 }, + { 1, 3, 35, 8, 229, 0, 16 }, + { 9, 0, 0, 8, 213, 17, 32 }, + { 0, 9, 15, 8, 196, 0, 16 }, + { 0, 11, 17, 8, 196, 0, 16 }, + { 0, 15, 9, 8, 196, 0, 16 }, + { 0, 17, 11, 8, 196, 0, 16 }, + { 1, 1, 33, 8, 196, 0, 16 }, + { 1, 3, 35, 8, 196, 0, 16 }, + { 9, 0, 0, 8, 17, 16, 228 }, + { 10, 9, 15, 8, 245, 0, 0 }, + { 10, 11, 17, 8, 245, 0, 0 }, + { 10, 15, 9, 8, 245, 0, 0 }, + { 10, 17, 11, 8, 245, 0, 0 }, + { 11, 1, 33, 8, 245, 0, 0 }, + { 11, 3, 35, 8, 245, 0, 0 }, + { 12, 0, 54, 8, 244, 0, 0 }, + { 13, 0, 54, 8, 0, 0, 0 }, + { 14, 0, 54, 8, 0, 0, 0 }, + { 15, 0, 0, 8, 0, 0, 0 }, + { 16, 42, 11, 8, 0, 0, 0 }, + { 10, 10, 16, 8, 64, 0, 0 }, + { 13, 0, 3, 8, 0, 0, 0 }, + { 17, 17, 11, 8, 33, 0, 212 }, + { 18, 0, 5, 8, 0, 0, 0 }, + { 19, 59, 56, 8, 0, 8, 0 }, + { 20, 59, 56, 8, 0, 8, 0 }, + { 19, 55, 59, 8, 0, 8, 0 }, + { 20, 55, 59, 8, 0, 8, 0 }, + { 13, 0, 40, 13, 0, 32, 0 }, + { 13, 0, 40, 13, 0, 1, 0 }, + { 13, 0, 40, 13, 0, 64, 0 }, + { 13, 0, 40, 13, 0, 65, 0 }, + { 13, 0, 40, 13, 0, 128, 0 }, + { 13, 0, 40, 13, 0, 4, 0 }, + { 13, 0, 40, 13, 0, 160, 0 }, + { 13, 0, 40, 13, 0, 224, 0 }, + { 10, 9, 15, 8, 196, 0, 16 }, + { 10, 11, 17, 8, 196, 0, 16 }, + { 0, 9, 15, 8, 0, 0, 0 }, + { 0, 11, 17, 8, 0, 0, 0 }, + { 21, 9, 15, 8, 0, 0, 0 }, + { 21, 11, 17, 8, 0, 0, 0 }, + { 21, 15, 9, 8, 0, 0, 0 }, + { 21, 17, 11, 8, 0, 0, 0 }, + { 21, 31, 28, 8, 0, 0, 0 }, + { 21, 42, 11, 8, 0, 0, 0 }, + { 21, 28, 31, 8, 0, 0, 0 }, + { 1, 35, 54, 8, 0, 0, 0 }, + { 22, 0, 0, 8, 0, 0, 0 }, + { 9, 0, 38, 9, 0, 0, 0 }, + { 23, 0, 0, 8, 0, 0, 0 }, + { 23, 0, 0, 8, 255, 0, 0 }, + { 11, 0, 0, 8, 213, 0, 0 }, + { 11, 0, 0, 8, 0, 0, 0 }, + { 1, 49, 33, 8, 0, 0, 0 }, + { 1, 50, 35, 8, 0, 0, 0 }, + { 1, 33, 49, 8, 0, 0, 0 }, + { 1, 35, 50, 8, 0, 0, 0 }, + { 24, 55, 56, 8, 0, 8, 0 }, + { 25, 55, 56, 8, 0, 8, 0 }, + { 19, 56, 55, 8, 245, 8, 0 }, + { 26, 56, 55, 8, 245, 8, 0 }, + { 11, 1, 33, 8, 196, 0, 16 }, + { 11, 3, 35, 8, 196, 0, 16 }, + { 19, 33, 56, 8, 0, 8, 0 }, + { 26, 35, 56, 8, 0, 8, 0 }, + { 19, 55, 33, 8, 0, 8, 0 }, + { 26, 55, 35, 8, 0, 8, 0 }, + { 19, 33, 56, 8, 245, 8, 0 }, + { 26, 35, 56, 8, 245, 8, 0 }, + { 1, 1, 53, 8, 0, 0, 0 }, + { 27, 3, 54, 8, 0, 0, 0 }, + { 13, 0, 2, 10, 0, 0, 0 }, + { 13, 0, 0, 10, 0, 0, 0 }, + { 16, 37, 11, 8, 0, 0, 0 }, + { 13, 8, 6, 8, 0, 0, 0 }, + { 13, 0, 0, 8, 0, 0, 0 }, + { 28, 0, 2, 10, 0, 0, 0 }, + { 28, 0, 0, 10, 0, 0, 0 }, + { 11, 0, 0, 14, 0, 0, 0 }, + { 11, 0, 1, 14, 0, 0, 0 }, + { 9, 0, 0, 14, 0, 0, 0 }, + { 28, 0, 0, 10, 255, 0, 0 }, + { 9, 0, 1, 8, 196, 0, 49 }, + { 9, 0, 0, 8, 0, 0, 0 }, + { 29, 0, 57, 8, 0, 0, 0 }, + { 30, 0, 40, 13, 0, 64, 0 }, + { 30, 0, 40, 13, 0, 0, 0 }, + { 31, 0, 40, 13, 0, 0, 0 }, + { 1, 1, 33, 8, 0, 0, 0 }, + { 1, 1, 36, 8, 0, 0, 0 }, + { 11, 33, 1, 8, 0, 0, 0 }, + { 11, 36, 1, 8, 0, 0, 0 }, + { 13, 0, 41, 9, 0, 0, 0 }, + { 13, 0, 41, 12, 0, 0, 0 }, + { 9, 0, 38, 12, 0, 0, 0 }, + { 13, 0, 40, 12, 0, 0, 0 }, + { 1, 59, 33, 8, 0, 0, 0 }, + { 1, 59, 36, 8, 0, 0, 0 }, + { 11, 33, 59, 8, 0, 0, 0 }, + { 11, 36, 59, 8, 0, 0, 0 }, + { 11, 0, 0, 8, 1, 0, 0 }, + { 11, 0, 0, 8, 2, 0, 0 }, + { 11, 0, 0, 8, 8, 0, 0 }, + { 10, 16, 11, 8, 64, 0, 0 }, + { 32, 0, 0, 27, 0, 0, 0 }, + { 32, 0, 0, 8, 0, 0, 0 }, + { 32, 0, 0, 14, 0, 0, 0 }, + { 11, 0, 0, 96, 0, 0, 0 }, + { 10, 0, 17, 8, 0, 0, 0 }, + { 33, 29, 14, 8, 0, 0, 0 }, + { 33, 30, 14, 8, 0, 0, 0 }, + { 33, 14, 29, 8, 0, 0, 0 }, + { 33, 14, 30, 8, 0, 0, 0 }, + { 34, 0, 0, 8, 0, 0, 0 }, + { 35, 17, 11, 31, 0, 32, 0 }, + { 35, 17, 11, 31, 0, 1, 0 }, + { 35, 17, 11, 31, 0, 64, 0 }, + { 35, 17, 11, 31, 0, 65, 0 }, + { 35, 17, 11, 31, 0, 128, 0 }, + { 35, 17, 11, 31, 0, 4, 0 }, + { 35, 17, 11, 31, 0, 160, 0 }, + { 35, 17, 11, 31, 0, 224, 0 }, + { 32, 0, 41, 13, 0, 32, 0 }, + { 32, 0, 41, 13, 0, 1, 0 }, + { 32, 0, 41, 13, 0, 64, 0 }, + { 32, 0, 41, 13, 0, 65, 0 }, + { 32, 0, 41, 13, 0, 128, 0 }, + { 32, 0, 41, 13, 0, 4, 0 }, + { 32, 0, 41, 13, 0, 160, 0 }, + { 32, 0, 41, 13, 0, 224, 0 }, + { 35, 0, 15, 8, 0, 32, 0 }, + { 35, 0, 15, 8, 0, 1, 0 }, + { 35, 0, 15, 8, 0, 64, 0 }, + { 35, 0, 15, 8, 0, 65, 0 }, + { 35, 0, 15, 8, 0, 128, 0 }, + { 35, 0, 15, 8, 0, 4, 0 }, + { 35, 0, 15, 8, 0, 160, 0 }, + { 35, 0, 15, 8, 0, 224, 0 }, + { 36, 0, 32, 8, 0, 0, 0 }, + { 37, 0, 32, 8, 0, 0, 0 }, + { 35, 11, 17, 8, 1, 0, 244 }, + { 38, 11, 17, 8, 197, 0, 48 }, + { 39, 0, 32, 8, 0, 0, 0 }, + { 40, 0, 32, 8, 0, 0, 0 }, + { 32, 0, 0, 8, 255, 0, 0 }, + { 41, 11, 17, 8, 1, 0, 244 }, + { 35, 17, 11, 8, 33, 0, 212 }, + { 41, 9, 15, 8, 245, 0, 0 }, + { 41, 11, 17, 8, 245, 0, 0 }, + { 42, 37, 11, 8, 0, 0, 0 }, + { 35, 15, 11, 8, 0, 0, 0 }, + { 43, 16, 11, 8, 0, 0, 0 }, + { 43, 13, 45, 48, 0, 0, 0 }, + { 44, 0, 54, 8, 0, 0, 0 }, + { 45, 1, 15, 8, 245, 0, 0 }, + { 45, 1, 15, 8, 196, 16, 0 }, + { 45, 1, 15, 8, 245, 1, 0 }, + { 45, 1, 15, 8, 229, 0, 16 }, + { 45, 1, 15, 8, 196, 0, 16 }, + { 46, 1, 15, 8, 245, 0, 0 }, + { 45, 3, 17, 8, 245, 0, 0 }, + { 45, 3, 17, 8, 196, 16, 0 }, + { 45, 3, 17, 8, 245, 1, 0 }, + { 45, 3, 17, 8, 229, 0, 16 }, + { 45, 3, 17, 8, 196, 0, 16 }, + { 46, 3, 17, 8, 245, 0, 0 }, + { 47, 1, 15, 8, 245, 0, 0 }, + { 47, 1, 15, 8, 196, 16, 0 }, + { 47, 1, 15, 8, 245, 1, 0 }, + { 47, 1, 15, 8, 229, 0, 16 }, + { 47, 1, 15, 8, 196, 0, 16 }, + { 48, 1, 15, 8, 245, 0, 0 }, + { 45, 5, 17, 8, 245, 0, 0 }, + { 49, 5, 17, 8, 196, 16, 0 }, + { 45, 5, 17, 8, 245, 1, 0 }, + { 49, 5, 17, 8, 229, 0, 16 }, + { 49, 5, 17, 8, 196, 0, 16 }, + { 46, 5, 17, 8, 245, 0, 0 }, + { 50, 0, 17, 8, 0, 0, 0 }, + { 51, 1, 15, 8, 1, 0, 32 }, + { 51, 1, 15, 8, 1, 1, 32 }, + { 51, 1, 15, 8, 197, 0, 48 }, + { 51, 1, 17, 8, 1, 0, 32 }, + { 51, 1, 17, 8, 1, 1, 32 }, + { 51, 1, 17, 8, 197, 0, 48 }, + { 52, 1, 15, 8, 0, 0, 0 }, + { 53, 0, 1, 24, 0, 0, 0 }, + { 52, 3, 17, 8, 0, 0, 0 }, + { 53, 0, 41, 24, 0, 0, 0 }, + { 51, 51, 15, 8, 33, 0, 0 }, + { 51, 51, 15, 8, 33, 1, 0 }, + { 51, 51, 15, 8, 229, 0, 16 }, + { 51, 51, 17, 8, 33, 0, 0 }, + { 51, 51, 17, 8, 33, 1, 0 }, + { 51, 51, 17, 8, 229, 0, 16 }, + { 51, 52, 15, 8, 1, 0, 32 }, + { 51, 52, 15, 8, 1, 1, 32 }, + { 51, 52, 15, 8, 197, 0, 48 }, + { 51, 52, 17, 8, 1, 0, 32 }, + { 51, 52, 17, 8, 1, 1, 32 }, + { 51, 52, 17, 8, 197, 0, 48 }, + { 46, 0, 21, 16, 0, 0, 0 }, + { 54, 0, 62, 16, 0, 0, 0 }, + { 54, 0, 61, 16, 0, 0, 0 }, + { 54, 0, 0, 16, 0, 0, 0 }, + { 51, 0, 21, 16, 0, 0, 0 }, + { 46, 0, 42, 16, 0, 0, 0 }, + { 46, 0, 20, 16, 0, 0, 0 }, + { 55, 0, 62, 24, 0, 1, 0 }, + { 55, 0, 62, 24, 0, 64, 0 }, + { 55, 0, 62, 24, 0, 65, 0 }, + { 55, 0, 62, 24, 0, 4, 0 }, + { 56, 0, 21, 56, 0, 0, 0 }, + { 46, 0, 23, 16, 0, 0, 0 }, + { 51, 0, 23, 16, 0, 0, 0 }, + { 55, 0, 62, 16, 69, 0, 0 }, + { 55, 0, 62, 24, 69, 0, 0 }, + { 46, 0, 22, 16, 0, 0, 0 }, + { 54, 0, 63, 16, 0, 0, 0 }, + { 56, 0, 22, 56, 0, 0, 0 }, + { 51, 0, 22, 16, 0, 0, 0 }, + { 56, 0, 20, 56, 0, 0, 0 }, + { 51, 0, 20, 16, 0, 0, 0 }, + { 46, 1, 15, 8, 196, 0, 16 }, + { 45, 0, 15, 8, 0, 0, 0 }, + { 45, 0, 15, 8, 245, 0, 0 }, + { 51, 0, 15, 8, 33, 0, 212 }, + { 51, 0, 15, 8, 0, 0, 245 }, + { 46, 3, 17, 8, 196, 0, 16 }, + { 45, 0, 17, 8, 0, 0, 0 }, + { 45, 0, 17, 8, 245, 0, 0 }, + { 51, 0, 17, 8, 33, 0, 212 }, + { 51, 0, 17, 8, 0, 0, 245 }, + { 45, 0, 15, 8, 244, 0, 0 }, + { 45, 0, 17, 8, 244, 0, 0 }, + { 57, 0, 17, 9, 0, 0, 0 }, + { 58, 0, 37, 9, 0, 0, 0 }, + { 57, 0, 17, 12, 0, 0, 0 }, + { 58, 0, 37, 12, 0, 0, 0 }, + { 57, 0, 17, 8, 0, 0, 0 }, + { 46, 0, 17, 8, 0, 0, 0 }, + { 46, 0, 16, 8, 0, 0, 0 }, + { 56, 0, 16, 8, 0, 0, 0 }, + { 46, 0, 16, 8, 64, 0, 0 }, + { 57, 0, 39, 8, 0, 0, 0 }, + { 52, 0, 28, 8, 0, 0, 0 }, + { 59, 0, 16, 8, 0, 0, 0 }, + { 56, 0, 42, 8, 0, 0, 0 }, + { 55, 0, 0, 112, 0, 0, 0 }, + { 55, 0, 0, 8, 0, 0, 0 }, + { 13, 0, 0, 24, 0, 0, 0 }, + { 56, 0, 58, 120, 0, 0, 0 }, + { 55, 0, 0, 120, 0, 0, 0 }, + { 55, 0, 58, 120, 0, 0, 0 }, + { 55, 60, 58, 120, 0, 0, 0 }, + { 60, 0, 0, 8, 0, 0, 0 }, + { 56, 0, 42, 96, 0, 0, 0 }, + { 61, 67, 64, 104, 0, 0, 0 }, + { 61, 67, 64, 96, 0, 0, 0 }, + { 35, 73, 68, 40, 0, 0, 0 }, + { 35, 73, 68, 48, 0, 0, 0 }, + { 35, 71, 68, 40, 0, 0, 0 }, + { 35, 72, 68, 48, 0, 0, 0 }, + { 62, 90, 83, 128, 0, 0, 0 }, + { 63, 81, 68, 128, 0, 0, 0 }, + { 64, 44, 68, 128, 0, 0, 0 }, + { 64, 46, 68, 128, 0, 0, 0 }, + { 35, 68, 73, 40, 0, 0, 0 }, + { 35, 68, 73, 48, 0, 0, 0 }, + { 35, 68, 71, 40, 0, 0, 0 }, + { 35, 68, 72, 48, 0, 0, 0 }, + { 62, 83, 90, 128, 0, 0, 0 }, + { 64, 68, 44, 128, 0, 0, 0 }, + { 64, 68, 46, 128, 0, 0, 0 }, + { 65, 72, 68, 40, 0, 0, 0 }, + { 35, 46, 68, 48, 0, 0, 0 }, + { 35, 72, 68, 56, 0, 0, 0 }, + { 66, 81, 68, 128, 0, 0, 0 }, + { 67, 81, 68, 128, 0, 0, 0 }, + { 62, 89, 83, 128, 0, 0, 0 }, + { 35, 68, 46, 40, 0, 0, 0 }, + { 35, 68, 46, 48, 0, 0, 0 }, + { 62, 68, 46, 128, 0, 0, 0 }, + { 34, 73, 68, 40, 0, 0, 0 }, + { 34, 73, 68, 48, 0, 0, 0 }, + { 67, 88, 83, 128, 0, 0, 0 }, + { 35, 73, 68, 56, 0, 0, 0 }, + { 56, 0, 42, 40, 0, 0, 0 }, + { 34, 67, 68, 40, 0, 0, 0 }, + { 34, 67, 68, 48, 0, 0, 0 }, + { 42, 18, 68, 40, 0, 0, 0 }, + { 42, 18, 68, 48, 0, 0, 0 }, + { 35, 68, 47, 40, 0, 0, 0 }, + { 35, 68, 47, 48, 0, 0, 0 }, + { 35, 68, 44, 88, 0, 0, 0 }, + { 35, 68, 46, 88, 0, 0, 0 }, + { 62, 83, 92, 128, 0, 0, 0 }, + { 34, 72, 64, 40, 0, 0, 0 }, + { 34, 73, 64, 48, 0, 0, 0 }, + { 42, 71, 13, 40, 0, 0, 0 }, + { 42, 72, 13, 48, 0, 0, 0 }, + { 62, 80, 78, 128, 0, 0, 0 }, + { 34, 71, 68, 40, 69, 0, 0 }, + { 34, 72, 68, 48, 0, 0, 0 }, + { 62, 71, 68, 128, 0, 0, 0 }, + { 62, 72, 68, 128, 0, 0, 0 }, + { 68, 69, 12, 40, 0, 0, 0 }, + { 68, 69, 12, 48, 0, 0, 0 }, + { 69, 83, 13, 128, 0, 0, 0 }, + { 34, 71, 68, 40, 0, 0, 0 }, + { 34, 71, 68, 48, 0, 0, 0 }, + { 62, 91, 83, 128, 0, 0, 0 }, + { 62, 90, 68, 128, 0, 0, 0 }, + { 34, 66, 64, 32, 0, 0, 0 }, + { 34, 67, 64, 32, 0, 0, 0 }, + { 70, 18, 64, 32, 0, 0, 0 }, + { 70, 18, 68, 48, 0, 0, 0 }, + { 62, 79, 68, 128, 0, 0, 0 }, + { 35, 67, 64, 32, 0, 0, 0 }, + { 71, 67, 64, 40, 0, 0, 0 }, + { 71, 73, 68, 48, 0, 0, 0 }, + { 67, 73, 68, 128, 0, 0, 0 }, + { 32, 0, 0, 32, 0, 0, 0 }, + { 72, 0, 0, 128, 0, 0, 0 }, + { 73, 13, 18, 112, 0, 0, 0 }, + { 74, 7, 69, 88, 0, 0, 0 }, + { 75, 69, 68, 88, 0, 0, 0 }, + { 73, 18, 13, 112, 0, 0, 0 }, + { 34, 69, 68, 88, 0, 0, 0 }, + { 76, 69, 68, 88, 0, 0, 0 }, + { 32, 72, 68, 112, 0, 0, 0 }, + { 32, 68, 72, 112, 0, 0, 0 }, + { 34, 73, 68, 56, 0, 0, 0 }, + { 70, 64, 18, 32, 0, 0, 0 }, + { 70, 68, 18, 48, 0, 0, 0 }, + { 62, 68, 79, 128, 0, 0, 0 }, + { 35, 64, 67, 32, 0, 0, 0 }, + { 77, 0, 42, 8, 0, 0, 0 }, + { 78, 0, 43, 8, 0, 0, 0 }, + { 79, 0, 43, 8, 0, 0, 0 }, + { 80, 17, 11, 80, 64, 0, 0 }, + { 81, 1, 17, 8, 1, 0, 244 }, + { 49, 1, 17, 8, 1, 0, 244 }, + { 34, 17, 11, 8, 64, 0, 245 }, + { 82, 17, 11, 112, 0, 0, 0 }, + { 83, 17, 11, 8, 65, 0, 180 }, + { 84, 73, 68, 40, 0, 0, 0 }, + { 84, 73, 68, 48, 0, 0, 0 }, + { 84, 71, 68, 40, 0, 0, 0 }, + { 84, 72, 68, 48, 0, 0, 0 }, + { 85, 88, 83, 128, 0, 0, 0 }, + { 85, 81, 68, 128, 0, 0, 0 }, + { 71, 25, 64, 40, 0, 0, 0 }, + { 71, 25, 68, 48, 0, 0, 0 }, + { 86, 81, 68, 128, 0, 0, 0 }, + { 87, 65, 12, 40, 0, 0, 0 }, + { 71, 69, 12, 48, 0, 0, 0 }, + { 88, 68, 13, 128, 0, 0, 0 }, + { 71, 73, 68, 40, 0, 0, 0 }, + { 86, 88, 83, 128, 0, 0, 0 }, + { 89, 0, 48, 8, 64, 0, 0 }, + { 56, 0, 46, 112, 0, 0, 0 }, + { 68, 65, 68, 48, 0, 0, 0 }, + { 68, 69, 64, 48, 0, 0, 0 }, + { 62, 68, 72, 128, 0, 0, 0 }, + { 76, 65, 12, 40, 0, 0, 0 }, + { 76, 69, 12, 48, 0, 0, 0 }, + { 69, 68, 13, 128, 0, 0, 0 }, + { 34, 67, 64, 40, 0, 0, 0 }, + { 35, 64, 46, 40, 0, 0, 0 }, + { 34, 42, 68, 56, 0, 0, 0 }, + { 62, 92, 83, 128, 0, 0, 0 }, + { 34, 67, 64, 48, 0, 0, 0 }, + { 76, 65, 64, 40, 0, 0, 0 }, + { 76, 69, 68, 48, 0, 0, 0 }, + { 90, 69, 68, 128, 0, 0, 0 }, + { 51, 0, 42, 16, 0, 0, 0 }, + { 91, 0, 42, 16, 0, 0, 0 }, + { 91, 0, 20, 16, 0, 0, 0 }, + { 92, 0, 0, 16, 0, 0, 0 }, + { 93, 0, 34, 16, 0, 0, 0 }, + { 94, 0, 34, 16, 0, 0, 0 }, + { 34, 67, 64, 64, 0, 0, 0 }, + { 34, 73, 68, 64, 0, 0, 0 }, + { 71, 73, 68, 72, 0, 0, 0 }, + { 34, 73, 68, 80, 0, 0, 0 }, + { 62, 44, 83, 128, 0, 0, 0 }, + { 62, 46, 85, 128, 0, 0, 0 }, + { 62, 47, 85, 128, 0, 0, 0 }, + { 62, 73, 68, 128, 0, 0, 0 }, + { 34, 72, 68, 72, 0, 0, 0 }, + { 34, 71, 68, 72, 0, 0, 0 }, + { 34, 70, 68, 72, 0, 0, 0 }, + { 62, 70, 68, 128, 0, 0, 0 }, + { 34, 73, 68, 72, 0, 0, 0 }, + { 35, 47, 68, 72, 0, 0, 0 }, + { 62, 47, 68, 128, 0, 0, 0 }, + { 67, 88, 92, 128, 0, 0, 0 }, + { 73, 47, 13, 112, 0, 0, 0 }, + { 67, 88, 83, 136, 0, 0, 0 }, + { 67, 81, 68, 136, 0, 0, 0 }, + { 34, 73, 68, 152, 0, 0, 0 }, + { 62, 73, 68, 152, 0, 0, 0 }, + { 67, 81, 68, 152, 0, 0, 0 }, + { 35, 17, 11, 8, 0, 0, 0 }, + { 35, 15, 13, 80, 0, 0, 0 }, + { 35, 11, 17, 8, 0, 0, 0 }, + { 35, 17, 13, 80, 0, 0, 0 }, + { 67, 90, 83, 128, 0, 0, 0 }, + { 86, 87, 85, 128, 0, 0, 0 }, + { 71, 71, 68, 72, 0, 0, 0 }, + { 71, 72, 68, 72, 0, 0, 0 }, + { 71, 67, 64, 64, 0, 0, 0 }, + { 71, 73, 68, 64, 0, 0, 0 }, + { 71, 68, 26, 72, 0, 0, 0 }, + { 88, 68, 76, 128, 0, 0, 0 }, + { 71, 68, 27, 72, 0, 0, 0 }, + { 88, 68, 77, 128, 0, 0, 0 }, + { 95, 68, 18, 72, 0, 0, 0 }, + { 67, 68, 79, 128, 0, 0, 0 }, + { 71, 68, 18, 72, 0, 0, 0 }, + { 67, 68, 75, 128, 0, 0, 0 }, + { 67, 85, 73, 128, 0, 0, 0 }, + { 71, 24, 68, 72, 0, 0, 0 }, + { 95, 18, 68, 72, 0, 0, 0 }, + { 71, 73, 68, 144, 0, 0, 0 }, + { 86, 81, 68, 144, 0, 0, 0 }, + { 71, 73, 68, 80, 0, 0, 0 }, + { 71, 73, 68, 152, 0, 0, 0 }, + { 67, 73, 68, 152, 0, 0, 0 }, + { 96, 1, 65, 32, 0, 0, 0 }, + { 56, 1, 69, 48, 0, 0, 0 }, + { 97, 69, 81, 128, 0, 0, 0 }, + { 98, 0, 13, 112, 0, 0, 0 }, + { 64, 0, 44, 128, 0, 0, 0 }, + { 56, 0, 42, 112, 0, 0, 0 }, + { 99, 75, 13, 8, 0, 0, 0 }, + { 98, 0, 17, 8, 0, 0, 0 }, + { 100, 67, 64, 96, 0, 0, 0 } +}; + +uint16_t CmpMnemonicOffsets[8] = { + 0, 9, 18, 27, 39, 49, 59, 69 +}; +uint16_t VCmpMnemonicOffsets[32] = { + 0, 10, 20, 30, 43, 54, 65, 76, 87, 100, 111, 122, 135, 149, 159, 169, 181, 194, 207, 220, 235, 249, 263, 277, 290, 303, 317, 331, 347, 361, 374, 387 +}; diff --git a/source/distorm/insts.h b/source/distorm/insts.h new file mode 100644 index 0000000..946cacd --- /dev/null +++ b/source/distorm/insts.h @@ -0,0 +1,64 @@ +/* +insts.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef INSTS_H +#define INSTS_H + +#include "instructions.h" + + +/* Flags Table */ +extern _iflags FlagsTable[]; + +/* Root Trie DB */ +extern _InstSharedInfo InstSharedInfoTable[]; +extern _InstInfo InstInfos[]; +extern _InstInfoEx InstInfosEx[]; +extern _InstNode InstructionsTree[]; + +/* 3DNow! Trie DB */ +extern _InstNode Table_0F_0F; +/* AVX related: */ +extern _InstNode Table_0F, Table_0F_38, Table_0F_3A; + +/* + * The inst_lookup will return on of these two instructions according to the specified decoding mode. + * ARPL or MOVSXD on 64 bits is one byte instruction at index 0x63. + */ +extern _InstInfo II_MOVSXD; + +/* + * The NOP instruction can be prefixed by REX in 64bits, therefore we have to decide in runtime whether it's an XCHG or NOP instruction. + * If 0x90 is prefixed by a usable REX it will become XCHG, otherwise it will become a NOP. + * Also note that if it's prefixed by 0xf3, it becomes a Pause. + */ +extern _InstInfo II_NOP; +extern _InstInfo II_PAUSE; + +/* + * RDRAND and VMPTRLD share same 2.3 bytes opcode, and then alternates on the MOD bits, + * RDRAND is OT_FULL_REG while VMPTRLD is OT_MEM, and there's no such mixed type. + * So a hack into the inst_lookup was added for this decision, the DB isn't flexible enough. :( + */ +extern _InstInfo II_RDRAND; + +/* + * Used for letting the extract operand know the type of operands without knowing the + * instruction itself yet, because of the way those instructions work. + * See function instructions.c!inst_lookup_3dnow. + */ +extern _InstInfo II_3DNOW; + +/* Helper tables for pseudo compare mnemonics. */ +extern uint16_t CmpMnemonicOffsets[8]; /* SSE */ +extern uint16_t VCmpMnemonicOffsets[32]; /* AVX */ + +#endif /* INSTS_H */ diff --git a/source/distorm/mnemonics.c b/source/distorm/mnemonics.c new file mode 100644 index 0000000..3ade426 --- /dev/null +++ b/source/distorm/mnemonics.c @@ -0,0 +1,284 @@ +/* +mnemonics.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "distorm/mnemonics.h" + +#ifndef DISTORM_LIGHT + +const unsigned char _MNEMONICS[] = +"\x09" "UNDEFINED\0" "\x03" "ADD\0" "\x04" "PUSH\0" "\x03" "POP\0" "\x02" "OR\0" \ +"\x03" "ADC\0" "\x03" "SBB\0" "\x03" "AND\0" "\x03" "DAA\0" "\x03" "SUB\0" \ +"\x03" "DAS\0" "\x03" "XOR\0" "\x03" "AAA\0" "\x03" "CMP\0" "\x03" "AAS\0" \ +"\x03" "INC\0" "\x03" "DEC\0" "\x05" "PUSHA\0" "\x04" "POPA\0" "\x05" "BOUND\0" \ +"\x04" "ARPL\0" "\x04" "IMUL\0" "\x03" "INS\0" "\x04" "OUTS\0" "\x02" "JO\0" \ +"\x03" "JNO\0" "\x02" "JB\0" "\x03" "JAE\0" "\x02" "JZ\0" "\x03" "JNZ\0" "\x03" "JBE\0" \ +"\x02" "JA\0" "\x02" "JS\0" "\x03" "JNS\0" "\x02" "JP\0" "\x03" "JNP\0" "\x02" "JL\0" \ +"\x03" "JGE\0" "\x03" "JLE\0" "\x02" "JG\0" "\x04" "TEST\0" "\x04" "XCHG\0" \ +"\x03" "MOV\0" "\x03" "LEA\0" "\x03" "CBW\0" "\x04" "CWDE\0" "\x04" "CDQE\0" \ +"\x03" "CWD\0" "\x03" "CDQ\0" "\x03" "CQO\0" "\x08" "CALL FAR\0" "\x05" "PUSHF\0" \ +"\x04" "POPF\0" "\x04" "SAHF\0" "\x04" "LAHF\0" "\x04" "MOVS\0" "\x04" "CMPS\0" \ +"\x04" "STOS\0" "\x04" "LODS\0" "\x04" "SCAS\0" "\x03" "RET\0" "\x03" "LES\0" \ +"\x03" "LDS\0" "\x05" "ENTER\0" "\x05" "LEAVE\0" "\x04" "RETF\0" "\x05" "INT 3\0" \ +"\x03" "INT\0" "\x04" "INTO\0" "\x04" "IRET\0" "\x03" "AAM\0" "\x03" "AAD\0" \ +"\x04" "SALC\0" "\x04" "XLAT\0" "\x06" "LOOPNZ\0" "\x05" "LOOPZ\0" "\x04" "LOOP\0" \ +"\x04" "JCXZ\0" "\x05" "JECXZ\0" "\x05" "JRCXZ\0" "\x02" "IN\0" "\x03" "OUT\0" \ +"\x04" "CALL\0" "\x03" "JMP\0" "\x07" "JMP FAR\0" "\x04" "INT1\0" "\x03" "HLT\0" \ +"\x03" "CMC\0" "\x03" "CLC\0" "\x03" "STC\0" "\x03" "CLI\0" "\x03" "STI\0" \ +"\x03" "CLD\0" "\x03" "STD\0" "\x03" "LAR\0" "\x03" "LSL\0" "\x07" "SYSCALL\0" \ +"\x04" "CLTS\0" "\x06" "SYSRET\0" "\x04" "INVD\0" "\x06" "WBINVD\0" "\x03" "UD2\0" \ +"\x05" "FEMMS\0" "\x03" "NOP\0" "\x05" "WRMSR\0" "\x05" "RDTSC\0" "\x05" "RDMSR\0" \ +"\x05" "RDPMC\0" "\x08" "SYSENTER\0" "\x07" "SYSEXIT\0" "\x06" "GETSEC\0" "\x05" "CMOVO\0" \ +"\x06" "CMOVNO\0" "\x05" "CMOVB\0" "\x06" "CMOVAE\0" "\x05" "CMOVZ\0" "\x06" "CMOVNZ\0" \ +"\x06" "CMOVBE\0" "\x05" "CMOVA\0" "\x05" "CMOVS\0" "\x06" "CMOVNS\0" "\x05" "CMOVP\0" \ +"\x06" "CMOVNP\0" "\x05" "CMOVL\0" "\x06" "CMOVGE\0" "\x06" "CMOVLE\0" "\x05" "CMOVG\0" \ +"\x04" "SETO\0" "\x05" "SETNO\0" "\x04" "SETB\0" "\x05" "SETAE\0" "\x04" "SETZ\0" \ +"\x05" "SETNZ\0" "\x05" "SETBE\0" "\x04" "SETA\0" "\x04" "SETS\0" "\x05" "SETNS\0" \ +"\x04" "SETP\0" "\x05" "SETNP\0" "\x04" "SETL\0" "\x05" "SETGE\0" "\x05" "SETLE\0" \ +"\x04" "SETG\0" "\x05" "CPUID\0" "\x02" "BT\0" "\x04" "SHLD\0" "\x03" "RSM\0" \ +"\x03" "BTS\0" "\x04" "SHRD\0" "\x07" "CMPXCHG\0" "\x03" "LSS\0" "\x03" "BTR\0" \ +"\x03" "LFS\0" "\x03" "LGS\0" "\x05" "MOVZX\0" "\x03" "BTC\0" "\x05" "MOVSX\0" \ +"\x04" "XADD\0" "\x06" "MOVNTI\0" "\x05" "BSWAP\0" "\x03" "ROL\0" "\x03" "ROR\0" \ +"\x03" "RCL\0" "\x03" "RCR\0" "\x03" "SHL\0" "\x03" "SHR\0" "\x03" "SAL\0" \ +"\x03" "SAR\0" "\x06" "XABORT\0" "\x06" "XBEGIN\0" "\x04" "FADD\0" "\x04" "FMUL\0" \ +"\x04" "FCOM\0" "\x05" "FCOMP\0" "\x04" "FSUB\0" "\x05" "FSUBR\0" "\x04" "FDIV\0" \ +"\x05" "FDIVR\0" "\x03" "FLD\0" "\x03" "FST\0" "\x04" "FSTP\0" "\x06" "FLDENV\0" \ +"\x05" "FLDCW\0" "\x04" "FXCH\0" "\x04" "FNOP\0" "\x04" "FCHS\0" "\x04" "FABS\0" \ +"\x04" "FTST\0" "\x04" "FXAM\0" "\x04" "FLD1\0" "\x06" "FLDL2T\0" "\x06" "FLDL2E\0" \ +"\x05" "FLDPI\0" "\x06" "FLDLG2\0" "\x06" "FLDLN2\0" "\x04" "FLDZ\0" "\x05" "F2XM1\0" \ +"\x05" "FYL2X\0" "\x05" "FPTAN\0" "\x06" "FPATAN\0" "\x07" "FXTRACT\0" "\x06" "FPREM1\0" \ +"\x07" "FDECSTP\0" "\x07" "FINCSTP\0" "\x05" "FPREM\0" "\x07" "FYL2XP1\0" "\x05" "FSQRT\0" \ +"\x07" "FSINCOS\0" "\x07" "FRNDINT\0" "\x06" "FSCALE\0" "\x04" "FSIN\0" "\x04" "FCOS\0" \ +"\x05" "FIADD\0" "\x05" "FIMUL\0" "\x05" "FICOM\0" "\x06" "FICOMP\0" "\x05" "FISUB\0" \ +"\x06" "FISUBR\0" "\x05" "FIDIV\0" "\x06" "FIDIVR\0" "\x06" "FCMOVB\0" "\x06" "FCMOVE\0" \ +"\x07" "FCMOVBE\0" "\x06" "FCMOVU\0" "\x07" "FUCOMPP\0" "\x04" "FILD\0" "\x06" "FISTTP\0" \ +"\x04" "FIST\0" "\x05" "FISTP\0" "\x07" "FCMOVNB\0" "\x07" "FCMOVNE\0" "\x08" "FCMOVNBE\0" \ +"\x07" "FCMOVNU\0" "\x04" "FENI\0" "\x06" "FEDISI\0" "\x06" "FSETPM\0" "\x06" "FUCOMI\0" \ +"\x05" "FCOMI\0" "\x06" "FRSTOR\0" "\x05" "FFREE\0" "\x05" "FUCOM\0" "\x06" "FUCOMP\0" \ +"\x05" "FADDP\0" "\x05" "FMULP\0" "\x06" "FCOMPP\0" "\x06" "FSUBRP\0" "\x05" "FSUBP\0" \ +"\x06" "FDIVRP\0" "\x05" "FDIVP\0" "\x04" "FBLD\0" "\x05" "FBSTP\0" "\x07" "FUCOMIP\0" \ +"\x06" "FCOMIP\0" "\x03" "NOT\0" "\x03" "NEG\0" "\x03" "MUL\0" "\x03" "DIV\0" \ +"\x04" "IDIV\0" "\x04" "SLDT\0" "\x03" "STR\0" "\x04" "LLDT\0" "\x03" "LTR\0" \ +"\x04" "VERR\0" "\x04" "VERW\0" "\x04" "SGDT\0" "\x04" "SIDT\0" "\x04" "LGDT\0" \ +"\x04" "LIDT\0" "\x04" "SMSW\0" "\x04" "LMSW\0" "\x06" "INVLPG\0" "\x06" "VMCALL\0" \ +"\x08" "VMLAUNCH\0" "\x08" "VMRESUME\0" "\x06" "VMXOFF\0" "\x07" "MONITOR\0" \ +"\x05" "MWAIT\0" "\x06" "XGETBV\0" "\x06" "XSETBV\0" "\x06" "VMFUNC\0" "\x04" "XEND\0" \ +"\x05" "VMRUN\0" "\x07" "VMMCALL\0" "\x06" "VMLOAD\0" "\x06" "VMSAVE\0" "\x04" "STGI\0" \ +"\x04" "CLGI\0" "\x06" "SKINIT\0" "\x07" "INVLPGA\0" "\x06" "SWAPGS\0" "\x06" "RDTSCP\0" \ +"\x08" "PREFETCH\0" "\x09" "PREFETCHW\0" "\x05" "PI2FW\0" "\x05" "PI2FD\0" \ +"\x05" "PF2IW\0" "\x05" "PF2ID\0" "\x06" "PFNACC\0" "\x07" "PFPNACC\0" "\x07" "PFCMPGE\0" \ +"\x05" "PFMIN\0" "\x05" "PFRCP\0" "\x07" "PFRSQRT\0" "\x05" "PFSUB\0" "\x05" "PFADD\0" \ +"\x07" "PFCMPGT\0" "\x05" "PFMAX\0" "\x08" "PFRCPIT1\0" "\x08" "PFRSQIT1\0" \ +"\x06" "PFSUBR\0" "\x05" "PFACC\0" "\x07" "PFCMPEQ\0" "\x05" "PFMUL\0" "\x08" "PFRCPIT2\0" \ +"\x07" "PMULHRW\0" "\x06" "PSWAPD\0" "\x07" "PAVGUSB\0" "\x06" "MOVUPS\0" "\x06" "MOVUPD\0" \ +"\x05" "MOVSS\0" "\x05" "MOVSD\0" "\x07" "VMOVUPS\0" "\x07" "VMOVUPD\0" "\x06" "VMOVSS\0" \ +"\x06" "VMOVSD\0" "\x07" "MOVHLPS\0" "\x06" "MOVLPS\0" "\x06" "MOVLPD\0" "\x08" "MOVSLDUP\0" \ +"\x07" "MOVDDUP\0" "\x08" "VMOVHLPS\0" "\x07" "VMOVLPS\0" "\x07" "VMOVLPD\0" \ +"\x09" "VMOVSLDUP\0" "\x08" "VMOVDDUP\0" "\x08" "UNPCKLPS\0" "\x08" "UNPCKLPD\0" \ +"\x09" "VUNPCKLPS\0" "\x09" "VUNPCKLPD\0" "\x08" "UNPCKHPS\0" "\x08" "UNPCKHPD\0" \ +"\x09" "VUNPCKHPS\0" "\x09" "VUNPCKHPD\0" "\x07" "MOVLHPS\0" "\x06" "MOVHPS\0" \ +"\x06" "MOVHPD\0" "\x08" "MOVSHDUP\0" "\x08" "VMOVLHPS\0" "\x07" "VMOVHPS\0" \ +"\x07" "VMOVHPD\0" "\x09" "VMOVSHDUP\0" "\x0b" "PREFETCHNTA\0" "\x0a" "PREFETCHT0\0" \ +"\x0a" "PREFETCHT1\0" "\x0a" "PREFETCHT2\0" "\x06" "MOVAPS\0" "\x06" "MOVAPD\0" \ +"\x07" "VMOVAPS\0" "\x07" "VMOVAPD\0" "\x08" "CVTPI2PS\0" "\x08" "CVTPI2PD\0" \ +"\x08" "CVTSI2SS\0" "\x08" "CVTSI2SD\0" "\x09" "VCVTSI2SS\0" "\x09" "VCVTSI2SD\0" \ +"\x07" "MOVNTPS\0" "\x07" "MOVNTPD\0" "\x07" "MOVNTSS\0" "\x07" "MOVNTSD\0" \ +"\x08" "VMOVNTPS\0" "\x08" "VMOVNTPD\0" "\x09" "CVTTPS2PI\0" "\x09" "CVTTPD2PI\0" \ +"\x09" "CVTTSS2SI\0" "\x09" "CVTTSD2SI\0" "\x0a" "VCVTTSS2SI\0" "\x0a" "VCVTTSD2SI\0" \ +"\x08" "CVTPS2PI\0" "\x08" "CVTPD2PI\0" "\x08" "CVTSS2SI\0" "\x08" "CVTSD2SI\0" \ +"\x09" "VCVTSS2SI\0" "\x09" "VCVTSD2SI\0" "\x07" "UCOMISS\0" "\x07" "UCOMISD\0" \ +"\x08" "VUCOMISS\0" "\x08" "VUCOMISD\0" "\x06" "COMISS\0" "\x06" "COMISD\0" \ +"\x07" "VCOMISS\0" "\x07" "VCOMISD\0" "\x08" "MOVMSKPS\0" "\x08" "MOVMSKPD\0" \ +"\x09" "VMOVMSKPS\0" "\x09" "VMOVMSKPD\0" "\x06" "SQRTPS\0" "\x06" "SQRTPD\0" \ +"\x06" "SQRTSS\0" "\x06" "SQRTSD\0" "\x07" "VSQRTPS\0" "\x07" "VSQRTPD\0" "\x07" "VSQRTSS\0" \ +"\x07" "VSQRTSD\0" "\x07" "RSQRTPS\0" "\x07" "RSQRTSS\0" "\x08" "VRSQRTPS\0" \ +"\x08" "VRSQRTSS\0" "\x05" "RCPPS\0" "\x05" "RCPSS\0" "\x06" "VRCPPS\0" "\x06" "VRCPSS\0" \ +"\x05" "ANDPS\0" "\x05" "ANDPD\0" "\x06" "VANDPS\0" "\x06" "VANDPD\0" "\x06" "ANDNPS\0" \ +"\x06" "ANDNPD\0" "\x07" "VANDNPS\0" "\x07" "VANDNPD\0" "\x04" "ORPS\0" "\x04" "ORPD\0" \ +"\x05" "VORPS\0" "\x05" "VORPD\0" "\x05" "XORPS\0" "\x05" "XORPD\0" "\x06" "VXORPS\0" \ +"\x06" "VXORPD\0" "\x05" "ADDPS\0" "\x05" "ADDPD\0" "\x05" "ADDSS\0" "\x05" "ADDSD\0" \ +"\x06" "VADDPS\0" "\x06" "VADDPD\0" "\x06" "VADDSS\0" "\x06" "VADDSD\0" "\x05" "MULPS\0" \ +"\x05" "MULPD\0" "\x05" "MULSS\0" "\x05" "MULSD\0" "\x06" "VMULPS\0" "\x06" "VMULPD\0" \ +"\x06" "VMULSS\0" "\x06" "VMULSD\0" "\x08" "CVTPS2PD\0" "\x08" "CVTPD2PS\0" \ +"\x08" "CVTSS2SD\0" "\x08" "CVTSD2SS\0" "\x09" "VCVTPS2PD\0" "\x09" "VCVTPD2PS\0" \ +"\x09" "VCVTSS2SD\0" "\x09" "VCVTSD2SS\0" "\x08" "CVTDQ2PS\0" "\x08" "CVTPS2DQ\0" \ +"\x09" "CVTTPS2DQ\0" "\x09" "VCVTDQ2PS\0" "\x09" "VCVTPS2DQ\0" "\x0a" "VCVTTPS2DQ\0" \ +"\x05" "SUBPS\0" "\x05" "SUBPD\0" "\x05" "SUBSS\0" "\x05" "SUBSD\0" "\x06" "VSUBPS\0" \ +"\x06" "VSUBPD\0" "\x06" "VSUBSS\0" "\x06" "VSUBSD\0" "\x05" "MINPS\0" "\x05" "MINPD\0" \ +"\x05" "MINSS\0" "\x05" "MINSD\0" "\x06" "VMINPS\0" "\x06" "VMINPD\0" "\x06" "VMINSS\0" \ +"\x06" "VMINSD\0" "\x05" "DIVPS\0" "\x05" "DIVPD\0" "\x05" "DIVSS\0" "\x05" "DIVSD\0" \ +"\x06" "VDIVPS\0" "\x06" "VDIVPD\0" "\x06" "VDIVSS\0" "\x06" "VDIVSD\0" "\x05" "MAXPS\0" \ +"\x05" "MAXPD\0" "\x05" "MAXSS\0" "\x05" "MAXSD\0" "\x06" "VMAXPS\0" "\x06" "VMAXPD\0" \ +"\x06" "VMAXSS\0" "\x06" "VMAXSD\0" "\x09" "PUNPCKLBW\0" "\x0a" "VPUNPCKLBW\0" \ +"\x09" "PUNPCKLWD\0" "\x0a" "VPUNPCKLWD\0" "\x09" "PUNPCKLDQ\0" "\x0a" "VPUNPCKLDQ\0" \ +"\x08" "PACKSSWB\0" "\x09" "VPACKSSWB\0" "\x07" "PCMPGTB\0" "\x08" "VPCMPGTB\0" \ +"\x07" "PCMPGTW\0" "\x08" "VPCMPGTW\0" "\x07" "PCMPGTD\0" "\x08" "VPCMPGTD\0" \ +"\x08" "PACKUSWB\0" "\x09" "VPACKUSWB\0" "\x09" "PUNPCKHBW\0" "\x0a" "VPUNPCKHBW\0" \ +"\x09" "PUNPCKHWD\0" "\x0a" "VPUNPCKHWD\0" "\x09" "PUNPCKHDQ\0" "\x0a" "VPUNPCKHDQ\0" \ +"\x08" "PACKSSDW\0" "\x09" "VPACKSSDW\0" "\x0a" "PUNPCKLQDQ\0" "\x0b" "VPUNPCKLQDQ\0" \ +"\x0a" "PUNPCKHQDQ\0" "\x0b" "VPUNPCKHQDQ\0" "\x04" "MOVD\0" "\x04" "MOVQ\0" \ +"\x05" "VMOVD\0" "\x05" "VMOVQ\0" "\x06" "MOVDQA\0" "\x06" "MOVDQU\0" "\x07" "VMOVDQA\0" \ +"\x07" "VMOVDQU\0" "\x06" "PSHUFW\0" "\x06" "PSHUFD\0" "\x07" "PSHUFHW\0" "\x07" "PSHUFLW\0" \ +"\x07" "VPSHUFD\0" "\x08" "VPSHUFHW\0" "\x08" "VPSHUFLW\0" "\x07" "PCMPEQB\0" \ +"\x08" "VPCMPEQB\0" "\x07" "PCMPEQW\0" "\x08" "VPCMPEQW\0" "\x07" "PCMPEQD\0" \ +"\x08" "VPCMPEQD\0" "\x04" "EMMS\0" "\x0a" "VZEROUPPER\0" "\x08" "VZEROALL\0" \ +"\x06" "VMREAD\0" "\x05" "EXTRQ\0" "\x07" "INSERTQ\0" "\x07" "VMWRITE\0" "\x08" "CVTPH2PS\0" \ +"\x08" "CVTPS2PH\0" "\x06" "HADDPD\0" "\x06" "HADDPS\0" "\x07" "VHADDPD\0" \ +"\x07" "VHADDPS\0" "\x06" "HSUBPD\0" "\x06" "HSUBPS\0" "\x07" "VHSUBPD\0" "\x07" "VHSUBPS\0" \ +"\x05" "XSAVE\0" "\x07" "XSAVE64\0" "\x06" "LFENCE\0" "\x06" "XRSTOR\0" "\x08" "XRSTOR64\0" \ +"\x06" "MFENCE\0" "\x08" "XSAVEOPT\0" "\x0a" "XSAVEOPT64\0" "\x06" "SFENCE\0" \ +"\x07" "CLFLUSH\0" "\x06" "POPCNT\0" "\x03" "BSF\0" "\x05" "TZCNT\0" "\x03" "BSR\0" \ +"\x05" "LZCNT\0" "\x07" "CMPEQPS\0" "\x07" "CMPLTPS\0" "\x07" "CMPLEPS\0" "\x0a" "CMPUNORDPS\0" \ +"\x08" "CMPNEQPS\0" "\x08" "CMPNLTPS\0" "\x08" "CMPNLEPS\0" "\x08" "CMPORDPS\0" \ +"\x07" "CMPEQPD\0" "\x07" "CMPLTPD\0" "\x07" "CMPLEPD\0" "\x0a" "CMPUNORDPD\0" \ +"\x08" "CMPNEQPD\0" "\x08" "CMPNLTPD\0" "\x08" "CMPNLEPD\0" "\x08" "CMPORDPD\0" \ +"\x07" "CMPEQSS\0" "\x07" "CMPLTSS\0" "\x07" "CMPLESS\0" "\x0a" "CMPUNORDSS\0" \ +"\x08" "CMPNEQSS\0" "\x08" "CMPNLTSS\0" "\x08" "CMPNLESS\0" "\x08" "CMPORDSS\0" \ +"\x07" "CMPEQSD\0" "\x07" "CMPLTSD\0" "\x07" "CMPLESD\0" "\x0a" "CMPUNORDSD\0" \ +"\x08" "CMPNEQSD\0" "\x08" "CMPNLTSD\0" "\x08" "CMPNLESD\0" "\x08" "CMPORDSD\0" \ +"\x08" "VCMPEQPS\0" "\x08" "VCMPLTPS\0" "\x08" "VCMPLEPS\0" "\x0b" "VCMPUNORDPS\0" \ +"\x09" "VCMPNEQPS\0" "\x09" "VCMPNLTPS\0" "\x09" "VCMPNLEPS\0" "\x09" "VCMPORDPS\0" \ +"\x0b" "VCMPEQ_UQPS\0" "\x09" "VCMPNGEPS\0" "\x09" "VCMPNGTPS\0" "\x0b" "VCMPFALSEPS\0" \ +"\x0c" "VCMPNEQ_OQPS\0" "\x08" "VCMPGEPS\0" "\x08" "VCMPGTPS\0" "\x0a" "VCMPTRUEPS\0" \ +"\x0b" "VCMPEQ_OSPS\0" "\x0b" "VCMPLT_OQPS\0" "\x0b" "VCMPLE_OQPS\0" "\x0d" "VCMPUNORD_SPS\0" \ +"\x0c" "VCMPNEQ_USPS\0" "\x0c" "VCMPNLT_UQPS\0" "\x0c" "VCMPNLE_UQPS\0" "\x0b" "VCMPORD_SPS\0" \ +"\x0b" "VCMPEQ_USPS\0" "\x0c" "VCMPNGE_UQPS\0" "\x0c" "VCMPNGT_UQPS\0" "\x0e" "VCMPFALSE_OSPS\0" \ +"\x0c" "VCMPNEQ_OSPS\0" "\x0b" "VCMPGE_OQPS\0" "\x0b" "VCMPGT_OQPS\0" "\x0d" "VCMPTRUE_USPS\0" \ +"\x08" "VCMPEQPD\0" "\x08" "VCMPLTPD\0" "\x08" "VCMPLEPD\0" "\x0b" "VCMPUNORDPD\0" \ +"\x09" "VCMPNEQPD\0" "\x09" "VCMPNLTPD\0" "\x09" "VCMPNLEPD\0" "\x09" "VCMPORDPD\0" \ +"\x0b" "VCMPEQ_UQPD\0" "\x09" "VCMPNGEPD\0" "\x09" "VCMPNGTPD\0" "\x0b" "VCMPFALSEPD\0" \ +"\x0c" "VCMPNEQ_OQPD\0" "\x08" "VCMPGEPD\0" "\x08" "VCMPGTPD\0" "\x0a" "VCMPTRUEPD\0" \ +"\x0b" "VCMPEQ_OSPD\0" "\x0b" "VCMPLT_OQPD\0" "\x0b" "VCMPLE_OQPD\0" "\x0d" "VCMPUNORD_SPD\0" \ +"\x0c" "VCMPNEQ_USPD\0" "\x0c" "VCMPNLT_UQPD\0" "\x0c" "VCMPNLE_UQPD\0" "\x0b" "VCMPORD_SPD\0" \ +"\x0b" "VCMPEQ_USPD\0" "\x0c" "VCMPNGE_UQPD\0" "\x0c" "VCMPNGT_UQPD\0" "\x0e" "VCMPFALSE_OSPD\0" \ +"\x0c" "VCMPNEQ_OSPD\0" "\x0b" "VCMPGE_OQPD\0" "\x0b" "VCMPGT_OQPD\0" "\x0d" "VCMPTRUE_USPD\0" \ +"\x08" "VCMPEQSS\0" "\x08" "VCMPLTSS\0" "\x08" "VCMPLESS\0" "\x0b" "VCMPUNORDSS\0" \ +"\x09" "VCMPNEQSS\0" "\x09" "VCMPNLTSS\0" "\x09" "VCMPNLESS\0" "\x09" "VCMPORDSS\0" \ +"\x0b" "VCMPEQ_UQSS\0" "\x09" "VCMPNGESS\0" "\x09" "VCMPNGTSS\0" "\x0b" "VCMPFALSESS\0" \ +"\x0c" "VCMPNEQ_OQSS\0" "\x08" "VCMPGESS\0" "\x08" "VCMPGTSS\0" "\x0a" "VCMPTRUESS\0" \ +"\x0b" "VCMPEQ_OSSS\0" "\x0b" "VCMPLT_OQSS\0" "\x0b" "VCMPLE_OQSS\0" "\x0d" "VCMPUNORD_SSS\0" \ +"\x0c" "VCMPNEQ_USSS\0" "\x0c" "VCMPNLT_UQSS\0" "\x0c" "VCMPNLE_UQSS\0" "\x0b" "VCMPORD_SSS\0" \ +"\x0b" "VCMPEQ_USSS\0" "\x0c" "VCMPNGE_UQSS\0" "\x0c" "VCMPNGT_UQSS\0" "\x0e" "VCMPFALSE_OSSS\0" \ +"\x0c" "VCMPNEQ_OSSS\0" "\x0b" "VCMPGE_OQSS\0" "\x0b" "VCMPGT_OQSS\0" "\x0d" "VCMPTRUE_USSS\0" \ +"\x08" "VCMPEQSD\0" "\x08" "VCMPLTSD\0" "\x08" "VCMPLESD\0" "\x0b" "VCMPUNORDSD\0" \ +"\x09" "VCMPNEQSD\0" "\x09" "VCMPNLTSD\0" "\x09" "VCMPNLESD\0" "\x09" "VCMPORDSD\0" \ +"\x0b" "VCMPEQ_UQSD\0" "\x09" "VCMPNGESD\0" "\x09" "VCMPNGTSD\0" "\x0b" "VCMPFALSESD\0" \ +"\x0c" "VCMPNEQ_OQSD\0" "\x08" "VCMPGESD\0" "\x08" "VCMPGTSD\0" "\x0a" "VCMPTRUESD\0" \ +"\x0b" "VCMPEQ_OSSD\0" "\x0b" "VCMPLT_OQSD\0" "\x0b" "VCMPLE_OQSD\0" "\x0d" "VCMPUNORD_SSD\0" \ +"\x0c" "VCMPNEQ_USSD\0" "\x0c" "VCMPNLT_UQSD\0" "\x0c" "VCMPNLE_UQSD\0" "\x0b" "VCMPORD_SSD\0" \ +"\x0b" "VCMPEQ_USSD\0" "\x0c" "VCMPNGE_UQSD\0" "\x0c" "VCMPNGT_UQSD\0" "\x0e" "VCMPFALSE_OSSD\0" \ +"\x0c" "VCMPNEQ_OSSD\0" "\x0b" "VCMPGE_OQSD\0" "\x0b" "VCMPGT_OQSD\0" "\x0d" "VCMPTRUE_USSD\0" \ +"\x06" "PINSRW\0" "\x07" "VPINSRW\0" "\x06" "PEXTRW\0" "\x07" "VPEXTRW\0" "\x06" "SHUFPS\0" \ +"\x06" "SHUFPD\0" "\x07" "VSHUFPS\0" "\x07" "VSHUFPD\0" "\x09" "CMPXCHG8B\0" \ +"\x0a" "CMPXCHG16B\0" "\x07" "VMPTRST\0" "\x08" "ADDSUBPD\0" "\x08" "ADDSUBPS\0" \ +"\x09" "VADDSUBPD\0" "\x09" "VADDSUBPS\0" "\x05" "PSRLW\0" "\x06" "VPSRLW\0" \ +"\x05" "PSRLD\0" "\x06" "VPSRLD\0" "\x05" "PSRLQ\0" "\x06" "VPSRLQ\0" "\x05" "PADDQ\0" \ +"\x06" "VPADDQ\0" "\x06" "PMULLW\0" "\x07" "VPMULLW\0" "\x07" "MOVQ2DQ\0" "\x07" "MOVDQ2Q\0" \ +"\x08" "PMOVMSKB\0" "\x09" "VPMOVMSKB\0" "\x07" "PSUBUSB\0" "\x08" "VPSUBUSB\0" \ +"\x07" "PSUBUSW\0" "\x08" "VPSUBUSW\0" "\x06" "PMINUB\0" "\x07" "VPMINUB\0" \ +"\x04" "PAND\0" "\x05" "VPAND\0" "\x07" "PADDUSB\0" "\x08" "VPADDUSW\0" "\x07" "PADDUSW\0" \ +"\x06" "PMAXUB\0" "\x07" "VPMAXUB\0" "\x05" "PANDN\0" "\x06" "VPANDN\0" "\x05" "PAVGB\0" \ +"\x06" "VPAVGB\0" "\x05" "PSRAW\0" "\x06" "VPSRAW\0" "\x05" "PSRAD\0" "\x06" "VPSRAD\0" \ +"\x05" "PAVGW\0" "\x06" "VPAVGW\0" "\x07" "PMULHUW\0" "\x08" "VPMULHUW\0" "\x06" "PMULHW\0" \ +"\x07" "VPMULHW\0" "\x09" "CVTTPD2DQ\0" "\x08" "CVTDQ2PD\0" "\x08" "CVTPD2DQ\0" \ +"\x0a" "VCVTTPD2DQ\0" "\x09" "VCVTDQ2PD\0" "\x09" "VCVTPD2DQ\0" "\x06" "MOVNTQ\0" \ +"\x07" "MOVNTDQ\0" "\x08" "VMOVNTDQ\0" "\x06" "PSUBSB\0" "\x07" "VPSUBSB\0" \ +"\x06" "PSUBSW\0" "\x07" "VPSUBSW\0" "\x06" "PMINSW\0" "\x07" "VPMINSW\0" "\x03" "POR\0" \ +"\x04" "VPOR\0" "\x06" "PADDSB\0" "\x07" "VPADDSB\0" "\x06" "PADDSW\0" "\x07" "VPADDSW\0" \ +"\x06" "PMAXSW\0" "\x07" "VPMAXSW\0" "\x04" "PXOR\0" "\x05" "VPXOR\0" "\x05" "LDDQU\0" \ +"\x06" "VLDDQU\0" "\x05" "PSLLW\0" "\x06" "VPSLLW\0" "\x05" "PSLLD\0" "\x06" "VPSLLD\0" \ +"\x05" "PSLLQ\0" "\x06" "VPSLLQ\0" "\x07" "PMULUDQ\0" "\x08" "VPMULUDQ\0" "\x07" "PMADDWD\0" \ +"\x08" "VPMADDWD\0" "\x06" "PSADBW\0" "\x07" "VPSADBW\0" "\x08" "MASKMOVQ\0" \ +"\x0a" "MASKMOVDQU\0" "\x0b" "VMASKMOVDQU\0" "\x05" "PSUBB\0" "\x06" "VPSUBB\0" \ +"\x05" "PSUBW\0" "\x06" "VPSUBW\0" "\x05" "PSUBD\0" "\x06" "VPSUBD\0" "\x05" "PSUBQ\0" \ +"\x06" "VPSUBQ\0" "\x05" "PADDB\0" "\x06" "VPADDB\0" "\x05" "PADDW\0" "\x06" "VPADDW\0" \ +"\x05" "PADDD\0" "\x06" "VPADDD\0" "\x07" "FNSTENV\0" "\x06" "FSTENV\0" "\x06" "FNSTCW\0" \ +"\x05" "FSTCW\0" "\x06" "FNCLEX\0" "\x05" "FCLEX\0" "\x06" "FNINIT\0" "\x05" "FINIT\0" \ +"\x06" "FNSAVE\0" "\x05" "FSAVE\0" "\x06" "FNSTSW\0" "\x05" "FSTSW\0" "\x06" "PSHUFB\0" \ +"\x07" "VPSHUFB\0" "\x06" "PHADDW\0" "\x07" "VPHADDW\0" "\x06" "PHADDD\0" "\x07" "VPHADDD\0" \ +"\x07" "PHADDSW\0" "\x08" "VPHADDSW\0" "\x09" "PMADDUBSW\0" "\x0a" "VPMADDUBSW\0" \ +"\x06" "PHSUBW\0" "\x07" "VPHSUBW\0" "\x06" "PHSUBD\0" "\x07" "VPHSUBD\0" "\x07" "PHSUBSW\0" \ +"\x08" "VPHSUBSW\0" "\x06" "PSIGNB\0" "\x07" "VPSIGNB\0" "\x06" "PSIGNW\0" \ +"\x07" "VPSIGNW\0" "\x06" "PSIGND\0" "\x07" "VPSIGND\0" "\x08" "PMULHRSW\0" \ +"\x09" "VPMULHRSW\0" "\x09" "VPERMILPS\0" "\x09" "VPERMILPD\0" "\x07" "VTESTPS\0" \ +"\x07" "VTESTPD\0" "\x08" "PBLENDVB\0" "\x08" "BLENDVPS\0" "\x08" "BLENDVPD\0" \ +"\x05" "PTEST\0" "\x06" "VPTEST\0" "\x0c" "VBROADCASTSS\0" "\x0c" "VBROADCASTSD\0" \ +"\x0e" "VBROADCASTF128\0" "\x05" "PABSB\0" "\x06" "VPABSB\0" "\x05" "PABSW\0" \ +"\x06" "VPABSW\0" "\x05" "PABSD\0" "\x06" "VPABSD\0" "\x08" "PMOVSXBW\0" "\x09" "VPMOVSXBW\0" \ +"\x08" "PMOVSXBD\0" "\x09" "VPMOVSXBD\0" "\x08" "PMOVSXBQ\0" "\x09" "VPMOVSXBQ\0" \ +"\x08" "PMOVSXWD\0" "\x09" "VPMOVSXWD\0" "\x08" "PMOVSXWQ\0" "\x09" "VPMOVSXWQ\0" \ +"\x08" "PMOVSXDQ\0" "\x09" "VPMOVSXDQ\0" "\x06" "PMULDQ\0" "\x07" "VPMULDQ\0" \ +"\x07" "PCMPEQQ\0" "\x08" "VPCMPEQQ\0" "\x08" "MOVNTDQA\0" "\x09" "VMOVNTDQA\0" \ +"\x08" "PACKUSDW\0" "\x09" "VPACKUSDW\0" "\x0a" "VMASKMOVPS\0" "\x0a" "VMASKMOVPD\0" \ +"\x08" "PMOVZXBW\0" "\x09" "VPMOVZXBW\0" "\x08" "PMOVZXBD\0" "\x09" "VPMOVZXBD\0" \ +"\x08" "PMOVZXBQ\0" "\x09" "VPMOVZXBQ\0" "\x08" "PMOVZXWD\0" "\x09" "VPMOVZXWD\0" \ +"\x08" "PMOVZXWQ\0" "\x09" "VPMOVZXWQ\0" "\x08" "PMOVZXDQ\0" "\x09" "VPMOVZXDQ\0" \ +"\x07" "PCMPGTQ\0" "\x08" "VPCMPGTQ\0" "\x06" "PMINSB\0" "\x07" "VPMINSB\0" \ +"\x06" "PMINSD\0" "\x07" "VPMINSD\0" "\x06" "PMINUW\0" "\x07" "VPMINUW\0" "\x06" "PMINUD\0" \ +"\x07" "VPMINUD\0" "\x06" "PMAXSB\0" "\x07" "VPMAXSB\0" "\x06" "PMAXSD\0" "\x07" "VPMAXSD\0" \ +"\x06" "PMAXUW\0" "\x07" "VPMAXUW\0" "\x06" "PMAXUD\0" "\x07" "VPMAXUD\0" "\x06" "PMULLD\0" \ +"\x07" "VPMULLD\0" "\x0a" "PHMINPOSUW\0" "\x0b" "VPHMINPOSUW\0" "\x06" "INVEPT\0" \ +"\x07" "INVVPID\0" "\x07" "INVPCID\0" "\x0e" "VFMADDSUB132PS\0" "\x0e" "VFMADDSUB132PD\0" \ +"\x0e" "VFMSUBADD132PS\0" "\x0e" "VFMSUBADD132PD\0" "\x0b" "VFMADD132PS\0" \ +"\x0b" "VFMADD132PD\0" "\x0b" "VFMADD132SS\0" "\x0b" "VFMADD132SD\0" "\x0b" "VFMSUB132PS\0" \ +"\x0b" "VFMSUB132PD\0" "\x0b" "VFMSUB132SS\0" "\x0b" "VFMSUB132SD\0" "\x0c" "VFNMADD132PS\0" \ +"\x0c" "VFNMADD132PD\0" "\x0c" "VFNMADD132SS\0" "\x0c" "VFNMADD132SD\0" "\x0c" "VFNMSUB132PS\0" \ +"\x0c" "VFNMSUB132PD\0" "\x0c" "VFNMSUB132SS\0" "\x0c" "VFNMSUB132SD\0" "\x0e" "VFMADDSUB213PS\0" \ +"\x0e" "VFMADDSUB213PD\0" "\x0e" "VFMSUBADD213PS\0" "\x0e" "VFMSUBADD213PD\0" \ +"\x0b" "VFMADD213PS\0" "\x0b" "VFMADD213PD\0" "\x0b" "VFMADD213SS\0" "\x0b" "VFMADD213SD\0" \ +"\x0b" "VFMSUB213PS\0" "\x0b" "VFMSUB213PD\0" "\x0b" "VFMSUB213SS\0" "\x0b" "VFMSUB213SD\0" \ +"\x0c" "VFNMADD213PS\0" "\x0c" "VFNMADD213PD\0" "\x0c" "VFNMADD213SS\0" "\x0c" "VFNMADD213SD\0" \ +"\x0c" "VFNMSUB213PS\0" "\x0c" "VFNMSUB213PD\0" "\x0c" "VFNMSUB213SS\0" "\x0c" "VFNMSUB213SD\0" \ +"\x0e" "VFMADDSUB231PS\0" "\x0e" "VFMADDSUB231PD\0" "\x0e" "VFMSUBADD231PS\0" \ +"\x0e" "VFMSUBADD231PD\0" "\x0b" "VFMADD231PS\0" "\x0b" "VFMADD231PD\0" "\x0b" "VFMADD231SS\0" \ +"\x0b" "VFMADD231SD\0" "\x0b" "VFMSUB231PS\0" "\x0b" "VFMSUB231PD\0" "\x0b" "VFMSUB231SS\0" \ +"\x0b" "VFMSUB231SD\0" "\x0c" "VFNMADD231PS\0" "\x0c" "VFNMADD231PD\0" "\x0c" "VFNMADD231SS\0" \ +"\x0c" "VFNMADD231SD\0" "\x0c" "VFNMSUB231PS\0" "\x0c" "VFNMSUB231PD\0" "\x0c" "VFNMSUB231SS\0" \ +"\x0c" "VFNMSUB231SD\0" "\x06" "AESIMC\0" "\x07" "VAESIMC\0" "\x06" "AESENC\0" \ +"\x07" "VAESENC\0" "\x0a" "AESENCLAST\0" "\x0b" "VAESENCLAST\0" "\x06" "AESDEC\0" \ +"\x07" "VAESDEC\0" "\x0a" "AESDECLAST\0" "\x0b" "VAESDECLAST\0" "\x05" "MOVBE\0" \ +"\x05" "CRC32\0" "\x0a" "VPERM2F128\0" "\x07" "ROUNDPS\0" "\x08" "VROUNDPS\0" \ +"\x07" "ROUNDPD\0" "\x08" "VROUNDPD\0" "\x07" "ROUNDSS\0" "\x08" "VROUNDSS\0" \ +"\x07" "ROUNDSD\0" "\x08" "VROUNDSD\0" "\x07" "BLENDPS\0" "\x08" "VBLENDPS\0" \ +"\x07" "BLENDPD\0" "\x08" "VBLENDPD\0" "\x07" "PBLENDW\0" "\x08" "VPBLENDW\0" \ +"\x07" "PALIGNR\0" "\x08" "VPALIGNR\0" "\x06" "PEXTRB\0" "\x07" "VPEXTRB\0" \ +"\x06" "PEXTRD\0" "\x06" "PEXTRQ\0" "\x07" "VPEXTRD\0" "\x07" "VPEXTRQ\0" "\x09" "EXTRACTPS\0" \ +"\x0a" "VEXTRACTPS\0" "\x0b" "VINSERTF128\0" "\x0c" "VEXTRACTF128\0" "\x06" "PINSRB\0" \ +"\x07" "VPINSRB\0" "\x08" "INSERTPS\0" "\x09" "VINSERTPS\0" "\x06" "PINSRD\0" \ +"\x06" "PINSRQ\0" "\x07" "VPINSRD\0" "\x07" "VPINSRQ\0" "\x04" "DPPS\0" "\x05" "VDPPS\0" \ +"\x04" "DPPD\0" "\x05" "VDPPD\0" "\x07" "MPSADBW\0" "\x08" "VMPSADBW\0" "\x09" "PCLMULQDQ\0" \ +"\x0a" "VPCLMULQDQ\0" "\x09" "VBLENDVPS\0" "\x09" "VBLENDVPD\0" "\x09" "VPBLENDVB\0" \ +"\x09" "PCMPESTRM\0" "\x0a" "VPCMPESTRM\0" "\x09" "PCMPESTRI\0" "\x0a" "VPCMPESTRI\0" \ +"\x09" "PCMPISTRM\0" "\x0a" "VPCMPISTRM\0" "\x09" "PCMPISTRI\0" "\x0a" "VPCMPISTRI\0" \ +"\x0f" "AESKEYGENASSIST\0" "\x10" "VAESKEYGENASSIST\0" "\x06" "PSRLDQ\0" "\x07" "VPSRLDQ\0" \ +"\x06" "PSLLDQ\0" "\x07" "VPSLLDQ\0" "\x06" "FXSAVE\0" "\x08" "FXSAVE64\0" \ +"\x08" "RDFSBASE\0" "\x07" "FXRSTOR\0" "\x09" "FXRSTOR64\0" "\x08" "RDGSBASE\0" \ +"\x07" "LDMXCSR\0" "\x08" "WRFSBASE\0" "\x08" "VLDMXCSR\0" "\x07" "STMXCSR\0" \ +"\x08" "WRGSBASE\0" "\x08" "VSTMXCSR\0" "\x07" "VMPTRLD\0" "\x07" "VMCLEAR\0" \ +"\x05" "VMXON\0" "\x06" "MOVSXD\0" "\x05" "PAUSE\0" "\x04" "WAIT\0" "\x06" "RDRAND\0" \ +"\x06" "_3DNOW\0"; + +const _WRegister _REGISTERS[] = { + { 3, "RAX" }, { 3, "RCX" }, { 3, "RDX" }, { 3, "RBX" }, { 3, "RSP" }, { 3, "RBP" }, { 3, "RSI" }, { 3, "RDI" }, { 2, "R8" }, { 2, "R9" }, { 3, "R10" }, { 3, "R11" }, { 3, "R12" }, { 3, "R13" }, { 3, "R14" }, { 3, "R15" }, + { 3, "EAX" }, { 3, "ECX" }, { 3, "EDX" }, { 3, "EBX" }, { 3, "ESP" }, { 3, "EBP" }, { 3, "ESI" }, { 3, "EDI" }, { 3, "R8D" }, { 3, "R9D" }, { 4, "R10D" }, { 4, "R11D" }, { 4, "R12D" }, { 4, "R13D" }, { 4, "R14D" }, { 4, "R15D" }, + { 2, "AX" }, { 2, "CX" }, { 2, "DX" }, { 2, "BX" }, { 2, "SP" }, { 2, "BP" }, { 2, "SI" }, { 2, "DI" }, { 3, "R8W" }, { 3, "R9W" }, { 4, "R10W" }, { 4, "R11W" }, { 4, "R12W" }, { 4, "R13W" }, { 4, "R14W" }, { 4, "R15W" }, + { 2, "AL" }, { 2, "CL" }, { 2, "DL" }, { 2, "BL" }, { 2, "AH" }, { 2, "CH" }, { 2, "DH" }, { 2, "BH" }, { 3, "R8B" }, { 3, "R9B" }, { 4, "R10B" }, { 4, "R11B" }, { 4, "R12B" }, { 4, "R13B" }, { 4, "R14B" }, { 4, "R15B" }, + { 3, "SPL" }, { 3, "BPL" }, { 3, "SIL" }, { 3, "DIL" }, + { 2, "ES" }, { 2, "CS" }, { 2, "SS" }, { 2, "DS" }, { 2, "FS" }, { 2, "GS" }, + { 3, "RIP" }, + { 3, "ST0" }, { 3, "ST1" }, { 3, "ST2" }, { 3, "ST3" }, { 3, "ST4" }, { 3, "ST5" }, { 3, "ST6" }, { 3, "ST7" }, + { 3, "MM0" }, { 3, "MM1" }, { 3, "MM2" }, { 3, "MM3" }, { 3, "MM4" }, { 3, "MM5" }, { 3, "MM6" }, { 3, "MM7" }, + { 4, "XMM0" }, { 4, "XMM1" }, { 4, "XMM2" }, { 4, "XMM3" }, { 4, "XMM4" }, { 4, "XMM5" }, { 4, "XMM6" }, { 4, "XMM7" }, { 4, "XMM8" }, { 4, "XMM9" }, { 5, "XMM10" }, { 5, "XMM11" }, { 5, "XMM12" }, { 5, "XMM13" }, { 5, "XMM14" }, { 5, "XMM15" }, + { 4, "YMM0" }, { 4, "YMM1" }, { 4, "YMM2" }, { 4, "YMM3" }, { 4, "YMM4" }, { 4, "YMM5" }, { 4, "YMM6" }, { 4, "YMM7" }, { 4, "YMM8" }, { 4, "YMM9" }, { 5, "YMM10" }, { 5, "YMM11" }, { 5, "YMM12" }, { 5, "YMM13" }, { 5, "YMM14" }, { 5, "YMM15" }, + { 3, "CR0" }, { 0, "" }, { 3, "CR2" }, { 3, "CR3" }, { 3, "CR4" }, { 0, "" }, { 0, "" }, { 0, "" }, { 3, "CR8" }, + { 3, "DR0" }, { 3, "DR1" }, { 3, "DR2" }, { 3, "DR3" }, { 0, "" }, { 0, "" }, { 3, "DR6" }, { 3, "DR7" } +}; + +#endif /* DISTORM_LIGHT */ diff --git a/source/distorm/operands.c b/source/distorm/operands.c new file mode 100644 index 0000000..d7cf1a7 --- /dev/null +++ b/source/distorm/operands.c @@ -0,0 +1,1291 @@ +/* +operands.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "config.h" +#include "operands.h" +#include "x86defs.h" +#include "insts.h" +#include "distorm/mnemonics.h" +#include "compat.h" + + +/* Maps a register to its register-class mask. */ +uint32_t _REGISTERTORCLASS[] = /* Based on _RegisterType enumeration! */ +{RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15, + RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15, + RM_AX, RM_CX, RM_DX, RM_BX, RM_SP, RM_BP, RM_SI, RM_DI, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15, + RM_AX, RM_CX, RM_DX, RM_BX, RM_AX, RM_CX, RM_DX, RM_BX, RM_R8, RM_R9, RM_R10, RM_R11, RM_R12, RM_R13, RM_R14, RM_R15, + RM_SP, RM_BP, RM_SI, RM_DI, + 0, 0, 0, 0, 0, 0, + 0, + RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, RM_FPU, + RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, RM_MMX, + RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, RM_SSE, + RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, RM_AVX, + RM_CR, 0, RM_CR, RM_CR, RM_CR, 0, 0, 0, RM_CR, + RM_DR, RM_DR, RM_DR, RM_DR, 0, 0, RM_DR, RM_DR +}; + +typedef enum {OPERAND_SIZE_NONE = 0, OPERAND_SIZE8, OPERAND_SIZE16, OPERAND_SIZE32, OPERAND_SIZE64, OPERAND_SIZE80, OPERAND_SIZE128, OPERAND_SIZE256} _OperandSizeType; +static uint16_t _OPSIZETOINT[] = {0, 8, 16, 32, 64, 80, 128, 256}; + +/* A helper function to fix the 8 bits register if REX is used (to support SIL, DIL, etc). */ +static unsigned int _FASTCALL_ operands_fix_8bit_rex_base(unsigned int reg) +{ + if ((reg >= 4) && (reg < 8)) return reg + REGS8_REX_BASE - 4; + return reg + REGS8_BASE; +} + +/* A helper function to set operand's type and size. */ +static void _FASTCALL_ operands_set_ts(_Operand* op, _OperandType type, uint16_t size) +{ + op->type = type; + op->size = size; +} + +/* A helper function to set operand's type, size and index. */ +static void _FASTCALL_ operands_set_tsi(_Operand* op, _OperandType type, uint16_t size, unsigned int index) +{ + op->type = type; + op->index = (uint8_t)index; + op->size = size; +} + +/* A helper function to read an unsigned integer from the stream safely. */ +static int _FASTCALL_ read_stream_safe_uint(_CodeInfo* ci, void* result, unsigned int size) +{ + ci->codeLen -= size; + if (ci->codeLen < 0) return FALSE; + switch (size) + { + case 1: *(uint8_t*)result = *(uint8_t*)ci->code; break; + case 2: *(uint16_t*)result = RUSHORT(ci->code); break; + case 4: *(uint32_t*)result = RULONG(ci->code); break; + case 8: *(uint64_t*)result = RULLONG(ci->code); break; + } + ci->code += size; + return TRUE; +} + +/* A helper function to read a signed integer from the stream safely. */ +static int _FASTCALL_ read_stream_safe_sint(_CodeInfo* ci, int64_t* result, unsigned int size) +{ + ci->codeLen -= size; + if (ci->codeLen < 0) return FALSE; + switch (size) + { + case 1: *result = *(int8_t*)ci->code; break; + case 2: *result = RSHORT(ci->code); break; + case 4: *result = RLONG(ci->code); break; + case 8: *result = RLLONG(ci->code); break; + } + ci->code += size; + return TRUE; +} + +/* + * SIB decoding is the most confusing part when decoding IA-32 instructions. + * This explanation should clear up some stuff. + * + * ! When base == 5, use EBP as the base register ! + * if (rm == 4) { + * if mod == 01, decode SIB byte and ALSO read a 8 bits displacement. + * if mod == 10, decode SIB byte and ALSO read a 32 bits displacement. + * if mod == 11 <-- EXCEPTION, this is a general-purpose register and mustn't lead to SIB decoding! + * ; So far so good, now the confusing part comes in with mod == 0 and base=5, but no worry. + * if (mod == 00) { + * decode SIB byte WITHOUT any displacement. + * EXCEPTION!!! when base == 5, read a 32 bits displacement, but this time DO NOT use (EBP) BASE at all! + * } + * + * NOTE: base could specify None (no base register) if base==5 and mod==0, but then you also need DISP32. + * } + */ +static void operands_extract_sib(_DInst* di, _OperandNumberType opNum, + _PrefixState* ps, _DecodeType effAdrSz, + unsigned int sib, unsigned int mod) +{ + unsigned int scale = 0, index = 0, base = 0; + unsigned int vrex = ps->vrex; + uint8_t* pIndex = NULL; + + _Operand* op = &di->ops[opNum]; + + /* + * SIB bits: + * |7---6-5----3-2---0| + * |SCALE| INDEX| BASE| + * |------------------| + */ + scale = (sib >> 6) & 3; + index = (sib >> 3) & 7; + base = sib & 7; + + /* + * The following fields: base/index/scale/disp8/32 are ALL optional by specific rules! + * The idea here is to keep the indirection as a simple-memory type. + * Because the base is optional, and we might be left with only one index. + * So even if there's a base but no index, or vice versa, we end up with one index register. + */ + + /* In 64 bits the REX prefix might affect the index of the SIB byte. */ + if (vrex & PREFIX_EX_X) { + ps->usedPrefixes |= INST_PRE_REX; + index += EX_GPR_BASE; + } + + if (index == 4) { /* No index is used. Use SMEM. */ + op->type = O_SMEM; + pIndex = &op->index; + } else { + op->type = O_MEM; + pIndex = &di->base; + /* No base, unless it is updated below. E.G: [EAX*4] has no base reg. */ + } + + if (base != 5) { + if (vrex & PREFIX_EX_B) ps->usedPrefixes |= INST_PRE_REX; + *pIndex = effAdrSz == Decode64Bits ? REGS64_BASE : REGS32_BASE; + *pIndex += (uint8_t)(base + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0)); + } else if (mod != 0) { + /* + * if base == 5 then you have to decode according to MOD. + * mod(00) - disp32. + * mod(01) - disp8 + rBP + * mod(10) - disp32 + rBP + * mod(11) - not possible, it's a general-purpose register. + */ + + if (vrex & PREFIX_EX_B) ps->usedPrefixes |= INST_PRE_REX; + if (effAdrSz == Decode64Bits) *pIndex = REGS64_BASE + 5 + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0); + else *pIndex = REGS32_BASE + 5 + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0); + } else if (index == 4) { + /* 32bits displacement only. */ + op->type = O_DISP; + return; + } + + if (index != 4) { /* In 64 bits decoding mode, if index == R12, it's valid! */ + if (effAdrSz == Decode64Bits) op->index = (uint8_t)(REGS64_BASE + index); + else op->index = (uint8_t)(REGS32_BASE + index); + di->scale = scale != 0 ? (1 << scale) : 0; + } +} + +/* + * This seems to be the hardest part in decoding the operands. + * If you take a look carefully at Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte, + * you will understand it's easy to decode the operands. + + * First we check the DT, so we can decide according to which Table in the documentation we are supposed to decode. + * Then we follow the specific table whether it's 16 bits or 32/64 bits. + + * Don't forget that Operand Size AND Address Size prefixes may change the decoding! + + * Some instructions force the use of RM16 or other specific types, so take it into account. + */ +static int operands_extract_modrm(_CodeInfo* ci, + _DInst* di, _OpType type, + _OperandNumberType opNum, _PrefixState* ps, + _DecodeType effOpSz, _DecodeType effAdrSz, + int* lockableInstruction, unsigned int mod, unsigned int rm, + _iflags instFlags) +{ + unsigned int vrex = ps->vrex, sib = 0, base = 0; + _Operand* op = &di->ops[opNum]; + uint16_t size = 0; + + if (mod == 3) { + /* + * General-purpose register is handled the same way in 16/32/64 bits decoding modes. + * NOTE!! that we have to override the size of the register, since it was set earlier as Memory and not Register! + */ + op->type = O_REG; + /* Start with original size which was set earlier, some registers have same size of memory and depend on it. */ + size = op->size; + switch(type) + { + case OT_RFULL_M16: + case OT_RM_FULL: + switch (effOpSz) + { + case Decode16Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + size = 16; + rm += REGS16_BASE; + break; + case Decode32Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + size = 32; + rm += REGS32_BASE; + break; + case Decode64Bits: + /* A fix for SMSW RAX which use the REX prefix. */ + if (type == OT_RFULL_M16) ps->usedPrefixes |= INST_PRE_REX; + /* CALL NEAR/PUSH/POP defaults to 64 bits. --> INST_64BITS, REX isn't required, thus ignored anyways. */ + if (instFlags & INST_PRE_REX) ps->usedPrefixes |= INST_PRE_REX; + /* Include REX if used for REX.B. */ + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + size = 64; + rm += REGS64_BASE; + break; + } + break; + case OT_R32_64_M8: + /* FALL THROUGH, decode 32 or 64 bits register. */ + case OT_R32_64_M16: + /* FALL THROUGH, decode 32 or 64 bits register. */ + case OT_RM32_64: /* Take care specifically in MOVNTI/MOVD/CVT's instructions, making it _REG64 with REX or if they are promoted. */ + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + /* Is it a promoted instruction? (only INST_64BITS is set and REX isn't required.) */ + if ((ci->dt == Decode64Bits) && ((instFlags & (INST_64BITS | INST_PRE_REX)) == INST_64BITS)) { + size = 64; + rm += REGS64_BASE; + break; + } + /* Give a chance to REX.W. Because if it was a promoted instruction we don't care about REX.W anyways. */ + if (vrex & PREFIX_EX_W) { + ps->usedPrefixes |= INST_PRE_REX; + size = 64; + rm += REGS64_BASE; + } else { + size = 32; + rm += REGS32_BASE; + } + break; + case OT_RM16_32: /* Used only with MOVZXD instruction to support 16 bits operand. */ + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + /* Is it 16 bits operand size? */ + if (ps->decodedPrefixes & INST_PRE_OP_SIZE) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + size = 16; + rm += REGS16_BASE; + } else { + size = 32; + rm += REGS32_BASE; + } + break; + case OT_RM16: + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + rm += REGS16_BASE; + break; + case OT_RM8: + if (ps->prefixExtType == PET_REX) { + ps->usedPrefixes |= INST_PRE_REX; + rm = operands_fix_8bit_rex_base(rm + ((vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0)); + } else rm += REGS8_BASE; + break; + case OT_MM32: + case OT_MM64: + /* MMX doesn't support extended registers. */ + size = 64; + rm += MMXREGS_BASE; + break; + + case OT_XMM16: + case OT_XMM32: + case OT_XMM64: + case OT_XMM128: + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + size = 128; + rm += SSEREGS_BASE; + break; + + case OT_RM32: + case OT_R32_M8: + case OT_R32_M16: + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + size = 32; + rm += REGS32_BASE; + break; + + case OT_YMM256: + if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE; + rm += AVXREGS_BASE; + break; + case OT_YXMM64_256: + case OT_YXMM128_256: + if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE; + if (vrex & PREFIX_EX_L) { + size = 256; + rm += AVXREGS_BASE; + } else { + size = 128; + rm += SSEREGS_BASE; + } + break; + case OT_WXMM32_64: + case OT_LXMM64_128: + if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE; + size = 128; + rm += SSEREGS_BASE; + break; + + case OT_WRM32_64: + case OT_REG32_64_M8: + case OT_REG32_64_M16: + if (vrex & PREFIX_EX_B) rm += EX_GPR_BASE; + if (vrex & PREFIX_EX_W) { + size = 64; + rm += REGS64_BASE; + } else { + size = 32; + rm += REGS32_BASE; + } + break; + + default: return FALSE; + } + op->size = size; + op->index = (uint8_t)rm; + return TRUE; + } + + /* Memory indirection decoding ahead:) */ + + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + if (lockableInstruction && (ps->decodedPrefixes & INST_PRE_LOCK)) *lockableInstruction = TRUE; + + if (effAdrSz == Decode16Bits) { + /* Decoding according to Table 2-1. (16 bits) */ + if ((mod == 0) && (rm == 6)) { + /* 6 is a special case - only 16 bits displacement. */ + op->type = O_DISP; + di->dispSize = 16; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int16_t))) return FALSE; + } else { + /* + * Create the O_MEM for 16 bits indirection that requires 2 registers, E.G: [BS+SI]. + * or create O_SMEM for a single register indirection, E.G: [BP]. + */ + static uint8_t MODS[] = {R_BX, R_BX, R_BP, R_BP, R_SI, R_DI, R_BP, R_BX}; + static uint8_t MODS2[] = {R_SI, R_DI, R_SI, R_DI}; + if (rm < 4) { + op->type = O_MEM; + di->base = MODS[rm]; + op->index = MODS2[rm]; + } else { + op->type = O_SMEM; + op->index = MODS[rm]; + } + + if (mod == 1) { /* 8 bits displacement + indirection */ + di->dispSize = 8; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int8_t))) return FALSE; + } else if (mod == 2) { /* 16 bits displacement + indirection */ + di->dispSize = 16; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int16_t))) return FALSE; + } + } + + if ((rm == 2) || (rm == 3) || ((rm == 6) && (mod != 0))) { + /* BP's default segment is SS, so ignore it. */ + prefixes_use_segment(INST_PRE_SS, ps, ci->dt, di); + } else { + /* Ignore default DS segment. */ + prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di); + } + } else { /* Decode32Bits or Decode64Bits! */ + /* Remember that from a 32/64 bits ModR/M byte a SIB byte could follow! */ + if ((mod == 0) && (rm == 5)) { + + /* 5 is a special case - only 32 bits displacement, or RIP relative. */ + di->dispSize = 32; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int32_t))) return FALSE; + + if (ci->dt == Decode64Bits) { + /* In 64 bits decoding mode depsite of the address size, a RIP-relative address it is. */ + op->type = O_SMEM; + op->index = R_RIP; + di->flags |= FLAG_RIP_RELATIVE; + } else { + /* Absolute address: */ + op->type = O_DISP; + } + } else { + if (rm == 4) { + /* 4 is a special case - SIB byte + disp8/32 follows! */ + /* Read SIB byte. */ + if (!read_stream_safe_uint(ci, &sib, sizeof(int8_t))) return FALSE; + operands_extract_sib(di, opNum, ps, effAdrSz, sib, mod); + } else { + op->type = O_SMEM; + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + + if (effAdrSz == Decode64Bits) op->index = (uint8_t)(REGS64_BASE + rm); + else op->index = (uint8_t)(REGS32_BASE + rm); + } + + if (mod == 1) { + di->dispSize = 8; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int8_t))) return FALSE; + } else if ((mod == 2) || ((sib & 7) == 5)) { /* If there is no BASE, read DISP32! */ + di->dispSize = 32; + if (!read_stream_safe_sint(ci, (int64_t*)&di->disp, sizeof(int32_t))) return FALSE; + } + } + + /* Get the base register. */ + base = op->index; + if (di->base != R_NONE) base = di->base; + else if (di->scale >= 2) base = 0; /* If it's only an index but got scale, it's still DS. */ + /* Default for EBP/ESP is SS segment. 64 bits mode ignores DS anyway. */ + if ((base == R_EBP) || (base == R_ESP)) prefixes_use_segment(INST_PRE_SS, ps, ci->dt, di); + else prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di); + } + + return TRUE; +} + + +/* + * This function is reponsible to textually format a required operand according to its type. + * It is vital to understand that there are other operands than what the ModR/M byte specifies. + + * Only by decoding the operands of an instruction which got a LOCK prefix, we could tell whether it may use the LOCK prefix. + * According to Intel, LOCK prefix must precede some specific instructions AND in their memory destination operand form (which means first operand). + * LOCK INC EAX, would generate an exception, but LOCK INC [EAX] is alright. + * Also LOCK ADD BX, [BP] would generate an exception. + + * Return code: + * TRUE - continue parsing the instruction and its operands, everything went right 'till now. + * FALSE - not enough bytes, or invalid operands. + */ + +int operands_extract(_CodeInfo* ci, _DInst* di, _InstInfo* ii, + _iflags instFlags, _OpType type, _OperandNumberType opNum, + unsigned int modrm, _PrefixState* ps, _DecodeType effOpSz, + _DecodeType effAdrSz, int* lockableInstruction) +{ + int ret = 0; + unsigned int mod = 0, reg = 0, rm = 0, vexV = ps->vexV; + unsigned int vrex = ps->vrex, typeHandled = TRUE; + _Operand* op = &di->ops[opNum]; + + /* Used to indicate the size of the MEMORY INDIRECTION only. */ + _OperandSizeType opSize = OPERAND_SIZE_NONE; + + /* + * ModRM bits: + * |7-6-5--------3-2-0| + * |MOD|REG/OPCODE|RM | + * |------------------| + */ + mod = (modrm >> 6) & 3; /* Mode(register-indirection, disp8+reg+indirection, disp16+reg+indirection, general-purpose register) */ + reg = (modrm >> 3) & 7; /* Register(could be part of the opcode itself or general-purpose register) */ + rm = modrm & 7; /* Specifies which general-purpose register or disp+reg to use. */ + + /* -- Memory Indirection Operands (that cannot be a general purpose register) -- */ + switch (type) + { + case OT_MEM64_128: /* Used only by CMPXCHG8/16B. */ + /* Make a specific check when the type is OT_MEM64_128 since the lockable CMPXCHG8B uses this one... */ + if (lockableInstruction && (ps->decodedPrefixes & INST_PRE_LOCK)) *lockableInstruction = TRUE; + if (effOpSz == Decode64Bits) { + ps->usedPrefixes |= INST_PRE_REX; + opSize = OPERAND_SIZE128; + } else opSize = OPERAND_SIZE64; + break; + case OT_MEM32: opSize = OPERAND_SIZE32; break; + case OT_MEM32_64: + /* Used by MOVNTI. Default size is 32bits, 64bits with REX. */ + if (effOpSz == Decode64Bits) { + ps->usedPrefixes |= INST_PRE_REX; + opSize = OPERAND_SIZE64; + } else opSize = OPERAND_SIZE32; + break; + case OT_MEM64: opSize = OPERAND_SIZE64; break; + case OT_MEM128: opSize = OPERAND_SIZE128; break; + case OT_MEM16_FULL: /* The size indicates about the second item of the pair. */ + switch (effOpSz) + { + case Decode16Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + opSize = OPERAND_SIZE16; + break; + case Decode32Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + opSize = OPERAND_SIZE32; + break; + case Decode64Bits: + /* Mark usage of REX only if it was required. */ + if ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX)) ps->usedPrefixes |= INST_PRE_REX; + opSize = OPERAND_SIZE64; + break; + } + break; + case OT_MEM16_3264: /* The size indicates about the second item of the pair. */ + if (ci->dt == Decode64Bits) opSize = OPERAND_SIZE64; + else opSize = OPERAND_SIZE32; + break; + case OT_MEM_OPT: + /* Since the MEM is optional, only when mod != 3, then return true as if the operand was alright. */ + if (mod == 0x3) return TRUE; + break; + case OT_FPUM16: opSize = OPERAND_SIZE16; break; + case OT_FPUM32: opSize = OPERAND_SIZE32; break; + case OT_FPUM64: opSize = OPERAND_SIZE64; break; + case OT_FPUM80: opSize = OPERAND_SIZE80; break; + case OT_LMEM128_256: + if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256; + else opSize = OPERAND_SIZE128; + break; + case OT_MEM: /* Size is unknown, but still handled. */ break; + default: typeHandled = FALSE; break; + } + if (typeHandled) { + /* All of the above types can't use a general-purpose register (a MOD of 3)!. */ + if (mod == 0x3) { + if (lockableInstruction) *lockableInstruction = FALSE; + return FALSE; + } + op->size = _OPSIZETOINT[opSize]; + ret = operands_extract_modrm(ci, di, type, opNum, ps, effOpSz, effAdrSz, lockableInstruction, mod, rm, instFlags); + if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) { + di->usedRegistersMask |= _REGISTERTORCLASS[op->index]; + } + return ret; + } + + /* -- Memory Indirection Operands (that can be a register) -- */ + typeHandled = TRUE; + switch (type) + { + case OT_RM_FULL: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* PUSH/JMP/CALL are automatically promoted to 64 bits! */ + if (effOpSz == Decode32Bits) { + opSize = OPERAND_SIZE32; + break; + } else if (effOpSz == Decode64Bits) { + /* Mark usage of REX only if it was required. */ + if ((instFlags & INST_64BITS) == 0) ps->usedPrefixes |= INST_PRE_REX; + opSize = OPERAND_SIZE64; + break; + } + /* FALL THROUGH BECAUSE dt==Decoded16Bits @-<----*/ + case OT_RM16: + /* If we got here not from OT_RM16, then the prefix was used. */ + if (type != OT_RM16) ps->usedPrefixes |= INST_PRE_OP_SIZE; + opSize = OPERAND_SIZE16; + break; + case OT_RM32_64: + /* The default size is 32, which can be 64 with a REX only. */ + if (effOpSz == Decode64Bits) { + opSize = OPERAND_SIZE64; + /* Mark REX prefix as used if non-promoted instruction. */ + if ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX)) { + ps->usedPrefixes |= INST_PRE_REX; + } + } else opSize = OPERAND_SIZE32; + break; + case OT_RM16_32: + /* Ignore REX, it's either 32 or 16 bits RM. */ + if (ps->decodedPrefixes & INST_PRE_OP_SIZE) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* Assume: We are in 64bits when we have this operand used. */ + opSize = OPERAND_SIZE16; + } else opSize = OPERAND_SIZE32; + break; + case OT_WXMM32_64: + case OT_WRM32_64: + if (vrex & PREFIX_EX_W) opSize = OPERAND_SIZE64; + else opSize = OPERAND_SIZE32; + break; + case OT_YXMM64_256: + if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256; + else opSize = OPERAND_SIZE64; + break; + case OT_YXMM128_256: + if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE256; + else opSize = OPERAND_SIZE128; + break; + case OT_LXMM64_128: + if (vrex & PREFIX_EX_L) opSize = OPERAND_SIZE128; + else opSize = OPERAND_SIZE64; + break; + case OT_RFULL_M16: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + opSize = OPERAND_SIZE16; + break; + + case OT_RM8: + case OT_R32_M8: + case OT_R32_64_M8: + case OT_REG32_64_M8: + opSize = OPERAND_SIZE8; + break; + + case OT_XMM16: + case OT_R32_M16: + case OT_R32_64_M16: + case OT_REG32_64_M16: + opSize = OPERAND_SIZE16; + break; + + case OT_RM32: + case OT_MM32: + case OT_XMM32: + opSize = OPERAND_SIZE32; + break; + + case OT_MM64: + case OT_XMM64: + opSize = OPERAND_SIZE64; + break; + + case OT_XMM128: opSize = OPERAND_SIZE128; break; + case OT_YMM256: opSize = OPERAND_SIZE256; break; + default: typeHandled = FALSE; break; + } + if (typeHandled) { + /* Fill size of memory dereference for operand. */ + op->size = _OPSIZETOINT[opSize]; + ret = operands_extract_modrm(ci, di, type, opNum, ps, effOpSz, effAdrSz, lockableInstruction, mod, rm, instFlags); + if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) { + di->usedRegistersMask |= _REGISTERTORCLASS[op->index]; + } + return ret; + } + + /* Simple operand type (no ModRM byte). */ + switch (type) + { + case OT_IMM8: + operands_set_ts(op, O_IMM, 8); + if (!read_stream_safe_uint(ci, &di->imm.byte, sizeof(int8_t))) return FALSE; + break; + case OT_IMM_FULL: /* 16, 32 or 64, depends on prefixes. */ + if (effOpSz == Decode16Bits) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* FALL THROUGH */ + case OT_IMM16: /* Force 16 bits imm. */ + operands_set_ts(op, O_IMM, 16); + if (!read_stream_safe_uint(ci, &di->imm.word, sizeof(int16_t))) return FALSE; + break; + /* + * Extension: MOV imm64, requires REX. + * Make sure it needs the REX. + * REX must be present because op size function takes it into consideration. + */ + } else if ((effOpSz == Decode64Bits) && + ((instFlags & (INST_64BITS | INST_PRE_REX)) == (INST_64BITS | INST_PRE_REX))) { + ps->usedPrefixes |= INST_PRE_REX; + + operands_set_ts(op, O_IMM, 64); + if (!read_stream_safe_uint(ci, &di->imm.qword, sizeof(int64_t))) return FALSE; + break; + } else ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* FALL THROUGH BECAUSE dt==Decoded32Bits @-<----*/ + case OT_IMM32: + op->type = O_IMM; + if (ci->dt == Decode64Bits) { + /* + * Imm32 is sign extended to 64 bits! + * Originally the op size was 64, but later was changed to reflect real size of imm. + */ + op->size = 32; + /* Use this as an indicator that it should be signed extended. */ + di->flags |= FLAG_IMM_SIGNED; + if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int32_t))) return FALSE; + } else { + op->size = 32; + if (!read_stream_safe_uint(ci, &di->imm.dword, sizeof(int32_t))) return FALSE; + } + break; + case OT_SEIMM8: /* Sign extended immediate. */ + /* + * PUSH SEIMM8 can be prefixed by operand size: + * Input stream: 66, 6a, 55 + * 64bits DT: push small 55 + * 32bits DT: push small 55 + * 16bits DT: push large 55 + * small/large indicates the size of the eSP pointer advancement. + * Check the instFlags (ii->flags) if it can be operand-size-prefixed and if the prefix exists. + */ + op->type = O_IMM; + if ((instFlags & INST_PRE_OP_SIZE) && (ps->decodedPrefixes & INST_PRE_OP_SIZE)) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + switch (ci->dt) + { + case Decode16Bits: op->size = 32; break; + case Decode32Bits: + case Decode64Bits: + op->size = 16; + break; + } + } else op->size = 8; + di->flags |= FLAG_IMM_SIGNED; + if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int8_t))) return FALSE; + break; + case OT_IMM16_1: + operands_set_ts(op, O_IMM1, 16); + if (!read_stream_safe_uint(ci, &di->imm.ex.i1, sizeof(int16_t))) return FALSE; + break; + case OT_IMM8_1: + operands_set_ts(op, O_IMM1, 8); + if (!read_stream_safe_uint(ci, &di->imm.ex.i1, sizeof(int8_t))) return FALSE; + break; + case OT_IMM8_2: + operands_set_ts(op, O_IMM2, 8); + if (!read_stream_safe_uint(ci, &di->imm.ex.i2, sizeof(int8_t))) return FALSE; + break; + case OT_REG8: + operands_set_ts(op, O_REG, 8); + if (ps->prefixExtType) { + /* + * If REX prefix is valid then we will have to use low bytes. + * This is a PASSIVE behavior changer of REX prefix, it affects operands even if its value is 0x40 ! + */ + ps->usedPrefixes |= INST_PRE_REX; + op->index = (uint8_t)operands_fix_8bit_rex_base(reg + ((vrex & PREFIX_EX_R) ? EX_GPR_BASE : 0)); + } else op->index = (uint8_t)(REGS8_BASE + reg); + break; + case OT_REG16: + operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg); + break; + case OT_REG_FULL: + switch (effOpSz) + { + case Decode16Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg); + break; + case Decode32Bits: + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } else ps->usedPrefixes |= INST_PRE_OP_SIZE; + operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg); + break; + case Decode64Bits: /* rex must be presented. */ + ps->usedPrefixes |= INST_PRE_REX; + operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg + ((vrex & PREFIX_EX_R) ? EX_GPR_BASE : 0)); + break; + } + break; + case OT_REG32: + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg); + break; + case OT_REG32_64: /* Handle CVT's, MOVxX and MOVNTI instructions which could be extended to 64 bits registers with REX. */ + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + + /* Is it a promoted instruction? (only INST_64BITS is set and REX isn't required.) */ + if ((ci->dt == Decode64Bits) && ((instFlags & (INST_64BITS | INST_PRE_REX)) == INST_64BITS)) { + operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg); + break; + } + /* Give a chance to REX.W. Because if it was a promoted instruction we don't care about REX.W anyways. */ + if (vrex & PREFIX_EX_W) { + ps->usedPrefixes |= INST_PRE_REX; + operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg); + } else operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg); + break; + case OT_FREG32_64_RM: /* Force decoding mode. Used for MOV CR(n)/DR(n) which defaults to 64 bits operand size in 64 bits. */ + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + + if (ci->dt == Decode64Bits) operands_set_tsi(op, O_REG, 64, REGS64_BASE + rm); + else operands_set_tsi(op, O_REG, 32, REGS32_BASE + rm); + break; + case OT_MM: /* MMX register */ + operands_set_tsi(op, O_REG, 64, MMXREGS_BASE + reg); + break; + case OT_MM_RM: /* MMX register, this time from the RM field */ + operands_set_tsi(op, O_REG, 64, MMXREGS_BASE + rm); + break; + case OT_REGXMM0: /* Implicit XMM0 operand. */ + reg = 0; + vrex = 0; + /* FALL THROUGH */ + case OT_XMM: /* SSE register */ + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg); + break; + case OT_XMM_RM: /* SSE register, this time from the RM field */ + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + rm += EX_GPR_BASE; + } + operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + rm); + break; + case OT_CREG: + /* + * Don't parse if the reg exceeds the bounds of the array. + * Most of the CR's are not implemented, so if there's no matching string, the operand is invalid. + */ + if (vrex & PREFIX_EX_R) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } else if ((ci->dt == Decode32Bits) && (ps->decodedPrefixes & INST_PRE_LOCK)) { + /* + * NOTE: In 32 bits decoding mode, + * if the lock prefix is set before MOV CR(n) it will become the 4th bit of the REG field like REX.R in 64 bits. + */ + reg += EX_GPR_BASE; + ps->usedPrefixes |= INST_PRE_LOCK; + } + /* Ignore some registers which do not exist. */ + if ((reg >= CREGS_MAX) || (reg == 1) || ((reg >= 5) && (reg <= 7))) return FALSE; + + op->type = O_REG; + if (ci->dt == Decode64Bits) op->size = 64; + else op->size = 32; + op->index = (uint8_t)(CREGS_BASE + reg); + break; + case OT_DREG: + /* + * In 64 bits there are 16 debug registers. + * but accessing any of dr8-15 which aren't implemented will cause an #ud. + */ + if ((reg == 4) || (reg == 5) || (vrex & PREFIX_EX_R)) return FALSE; + + op->type = O_REG; + if (ci->dt == Decode64Bits) op->size = 64; + else op->size = 32; + op->index = (uint8_t)(DREGS_BASE + reg); + break; + case OT_SREG: /* Works with REG16 only! */ + /* If lockableInstruction pointer is non-null we know it's the first operand. */ + if (lockableInstruction && (reg == 1)) return FALSE; /* Can't MOV CS, <REG>. */ + /*Don't parse if the reg exceeds the bounds of the array. */ + if (reg <= SEG_REGS_MAX - 1) operands_set_tsi(op, O_REG, 16, SREGS_BASE + reg); + else return FALSE; + break; + case OT_SEG: + op->type = O_REG; + /* Size of reg is always 16, it's up to caller to zero extend it to operand size. */ + op->size = 16; + ps->usedPrefixes |= INST_PRE_OP_SIZE; + /* + * Extract the SEG from ii->flags this time!!! + * Check whether an operand size prefix is used. + */ + switch (instFlags & INST_PRE_SEGOVRD_MASK) + { + case INST_PRE_ES: op->index = R_ES; break; + case INST_PRE_CS: op->index = R_CS; break; + case INST_PRE_SS: op->index = R_SS; break; + case INST_PRE_DS: op->index = R_DS; break; + case INST_PRE_FS: op->index = R_FS; break; + case INST_PRE_GS: op->index = R_GS; break; + } + break; + case OT_ACC8: + operands_set_tsi(op, O_REG, 8, R_AL); + break; + case OT_ACC16: + operands_set_tsi(op, O_REG, 16, R_AX); + break; + case OT_ACC_FULL_NOT64: /* No REX.W support for IN/OUT. */ + vrex &= ~PREFIX_EX_W; + case OT_ACC_FULL: + if (effOpSz == Decode16Bits) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + operands_set_tsi(op, O_REG, 16, R_AX); + } else if (effOpSz == Decode32Bits) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + operands_set_tsi(op, O_REG, 32, R_EAX); + } else { /* Decode64Bits */ + /* Only non-promoted instructions need REX in order to decode in 64 bits. */ + /* MEM-OFFSET MOV's are NOT automatically promoted to 64 bits. */ + if (~instFlags & INST_64BITS) { + ps->usedPrefixes |= INST_PRE_REX; + } + operands_set_tsi(op, O_REG, 64, R_RAX); + } + break; + case OT_PTR16_FULL: + /* ptr16:full - full is size of operand size to read, therefore Operand Size Prefix affects this. So we need to handle it. */ + if (effOpSz == Decode16Bits) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + ci->codeLen -= sizeof(int16_t)*2; + if (ci->codeLen < 0) return FALSE; + + operands_set_ts(op, O_PTR, 16); + di->imm.ptr.off = RUSHORT(ci->code); /* Read offset first. */ + di->imm.ptr.seg = RUSHORT((ci->code + sizeof(int16_t))); /* And read segment. */ + + ci->code += sizeof(int16_t)*2; + } else { /* Decode32Bits, for Decode64Bits this instruction is invalid. */ + ps->usedPrefixes |= INST_PRE_OP_SIZE; + ci->codeLen -= sizeof(int32_t) + sizeof(int16_t); + if (ci->codeLen < 0) return FALSE; + + operands_set_ts(op, O_PTR, 32); + di->imm.ptr.off = RULONG(ci->code); /* Read 32bits offset this time. */ + di->imm.ptr.seg = RUSHORT((ci->code + sizeof(int32_t))); /* And read segment, 16 bits. */ + + ci->code += sizeof(int32_t) + sizeof(int16_t); + } + break; + case OT_RELCB: + case OT_RELC_FULL: + + if (type == OT_RELCB) { + operands_set_ts(op, O_PC, 8); + if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int8_t))) return FALSE; + } else { /* OT_RELC_FULL */ + + /* Yep, operand size prefix affects relc also. */ + ps->usedPrefixes |= INST_PRE_OP_SIZE; + if (effOpSz == Decode16Bits) { + operands_set_ts(op, O_PC, 16); + if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int16_t))) return FALSE; + } else { /* Decode32Bits or Decode64Bits = for now they are the same */ + operands_set_ts(op, O_PC, 32); + if (!read_stream_safe_sint(ci, &di->imm.sqword, sizeof(int32_t))) return FALSE; + } + } + + /* Support for hint, see if there's a segment override. */ + if ((ii->opcodeId >= I_JO) && (ii->opcodeId <= I_JG)) { + if (ps->decodedPrefixes & INST_PRE_CS) { + ps->usedPrefixes |= INST_PRE_CS; + di->flags |= FLAG_HINT_NOT_TAKEN; + } else if (ps->decodedPrefixes & INST_PRE_DS) { + ps->usedPrefixes |= INST_PRE_DS; + di->flags |= FLAG_HINT_TAKEN; + } + } + break; + case OT_MOFFS8: + op->size = 8; + /* FALL THROUGH, size won't be changed. */ + case OT_MOFFS_FULL: + op->type = O_DISP; + if (op->size == 0) { + /* Calculate size of operand (same as ACC size). */ + switch (effOpSz) + { + case Decode16Bits: op->size = 16; break; + case Decode32Bits: op->size = 32; break; + case Decode64Bits: op->size = 64; break; + } + } + + prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di); + + /* + * Just a pointer to a BYTE, WORD, DWORD, QWORD. Works only with ACC8/16/32/64 respectively. + * MOV [0x1234], AL ; MOV AX, [0x1234] ; MOV EAX, [0x1234], note that R/E/AX will be chosen by OT_ACC_FULL. + */ + if (effAdrSz == Decode16Bits) { + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + + di->dispSize = 16; + if (!read_stream_safe_uint(ci, &di->disp, sizeof(int16_t))) return FALSE; + } else if (effAdrSz == Decode32Bits) { + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + + di->dispSize = 32; + if (!read_stream_safe_uint(ci, &di->disp, sizeof(int32_t))) return FALSE; + } else { /* Decode64Bits */ + di->dispSize = 64; + if (!read_stream_safe_uint(ci, &di->disp, sizeof(int64_t))) return FALSE; + } + break; + case OT_CONST1: + operands_set_ts(op, O_IMM, 8); + di->imm.byte = 1; + break; + case OT_REGCL: + operands_set_tsi(op, O_REG, 8, R_CL); + break; + + case OT_FPU_SI: + /* Low 3 bits specify the REG, similar to the MODR/M byte reg. */ + operands_set_tsi(op, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7)); + break; + case OT_FPU_SSI: + operands_set_tsi(op, O_REG, 32, R_ST0); + operands_set_tsi(op + 1, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7)); + break; + case OT_FPU_SIS: + operands_set_tsi(op, O_REG, 32, FPUREGS_BASE + (*(ci->code-1) & 7)); + operands_set_tsi(op + 1, O_REG, 32, R_ST0); + break; + + /* + * Special treatment for Instructions-Block: + * INC/DEC (only 16/32 bits) /PUSH/POP/XCHG instructions, which get their REG from their own binary code. + + * Notice these instructions are 1 or 2 byte long, + * code points after the byte which represents the instruction itself, + * thus, even if the instructions are 2 bytes long it will read its last byte which contains the REG info. + */ + case OT_IB_RB: + /* Low 3 bits specify the REG, similar to the MODR/M byte reg. */ + operands_set_ts(op, O_REG, 8); + reg = *(ci->code-1) & 7; + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + op->index = (uint8_t)operands_fix_8bit_rex_base(reg + EX_GPR_BASE); + } else if (ps->prefixExtType == PET_REX) { + ps->usedPrefixes |= INST_PRE_REX; + op->index = (uint8_t)operands_fix_8bit_rex_base(reg); + } else op->index = (uint8_t)(REGS8_BASE + reg); + break; + case OT_IB_R_FULL: + reg = *(ci->code-1) & 7; + switch (effOpSz) + { + case Decode16Bits: + ps->usedPrefixes |= INST_PRE_OP_SIZE; + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + operands_set_tsi(op, O_REG, 16, REGS16_BASE + reg); + break; + case Decode32Bits: + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } else ps->usedPrefixes |= INST_PRE_OP_SIZE; + operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg); + break; + case Decode64Bits: + /* + * Automatically promoted instruction can drop REX prefix if not required. + * PUSH/POP defaults to 64 bits. --> INST_64BITS + * MOV imm64 / BSWAP requires REX.W to be 64 bits --> INST_64BITS | INST_PRE_REX + */ + if ((instFlags & INST_64BITS) && ((instFlags & INST_PRE_REX) == 0)) { + if (vrex & PREFIX_EX_B) { + ps->usedPrefixes |= INST_PRE_REX; + reg += EX_GPR_BASE; + } + } else { + ps->usedPrefixes |= INST_PRE_REX; + reg += (vrex & PREFIX_EX_B) ? EX_GPR_BASE : 0; + } + operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg); + break; + } + break; + + /* + * Special treatment for repeatable instructions. + + * We want the following output: + * If there's only the REP/NZ prefix, we won't output anything (All operands are implicit). + * If there's an operand size prefix, we will change the suffix letter of the mnemonic, which specifies the size of operand to the required one. + * If there's a segment override prefix, we will output the segment and the used index register (EDI/ESI). + * If there's an address size prefix, we will output the (segment if needed and) the used and inverted index register (DI/SI). + + * Example: + * :: Decoding in 16 bits mode! :: + * AD ~ LODSW + * 66 AD ~ LODSD + * F3 AC ~ REP LODSB + * F3 66 AD ~ REP LODSD + * F3 3E AC ~ REP LODS BYTE DS:[SI] + * F3 67 AD ~ REP LODS WORD [ESI] + + * The basic form of a repeatable instruction has its operands hidden and has a suffix letter + * which implies on the size of operation being done. + * Therefore, we cannot change the mnemonic here when we encounter another prefix and its not the decoder's responsibility to do so. + * That's why the caller is responsible to add the suffix letter if no other prefixes are used. + * And all we are doing here is formatting the operand correctly. + */ + case OT_REGI_ESI: + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + + op->type = O_SMEM; + + /* This might be a 16, 32 or 64 bits instruction, depends on the decoding mode. */ + if (instFlags & INST_16BITS) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + + if (effOpSz == Decode16Bits) op->size = 16; + else if ((effOpSz == Decode64Bits) && (instFlags & INST_64BITS)) { + ps->usedPrefixes |= INST_PRE_REX; + op->size = 64; + } else op->size = 32; + } else op->size = 8; + + /* + * Clear segment in case OT_REGI_EDI was parsed earlier, + * DS can be overridden and therefore has precedence. + */ + di->segment = 0; + prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di); + + if (effAdrSz == Decode16Bits) op->index = R_SI; + else if (effAdrSz == Decode32Bits) op->index = R_ESI; + else op->index = R_RSI; + break; + case OT_REGI_EDI: + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + + op->type = O_SMEM; + + /* This might be a 16 or 32 bits instruction, depends on the decoding mode. */ + if (instFlags & INST_16BITS) { + ps->usedPrefixes |= INST_PRE_OP_SIZE; + + if (effOpSz == Decode16Bits) op->size = 16; + else if ((effOpSz == Decode64Bits) && (instFlags & INST_64BITS)) { + ps->usedPrefixes |= INST_PRE_REX; + op->size = 64; + } else op->size = 32; + } else op->size = 8; + + /* Note: The [rDI] operand can't be prefixed by a segment override, therefore we don't set usedPrefixes. */ + if ((opNum == ONT_1) && (ci->dt != Decode64Bits)) di->segment = R_ES | SEGMENT_DEFAULT; /* No ES in 64 bits mode. */ + + if (effAdrSz == Decode16Bits) op->index = R_DI; + else if (effAdrSz == Decode32Bits) op->index = R_EDI; + else op->index = R_RDI; + break; + + /* Used for In/Out instructions varying forms. */ + case OT_REGDX: + /* Simple single IN/OUT instruction. */ + operands_set_tsi(op, O_REG, 16, R_DX); + break; + + /* Used for INVLPGA instruction. */ + case OT_REGECX: + operands_set_tsi(op, O_REG, 32, R_ECX); + break; + case OT_REGI_EBXAL: + /* XLAT BYTE [rBX + AL] */ + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + + prefixes_use_segment(INST_PRE_DS, ps, ci->dt, di); + + /* Size of deref is always 8 for xlat. */ + operands_set_tsi(op, O_MEM, 8, R_AL); + + if (effAdrSz == Decode16Bits) di->base = R_BX; + else if (effAdrSz == Decode32Bits) di->base = R_EBX; + else { + ps->usedPrefixes |= INST_PRE_REX; + di->base = R_RBX; + } + break; + case OT_REGI_EAX: + /* + * Implicit rAX as memory indirection operand. Used by AMD's SVM instructions. + * Since this is a memory indirection, the default address size in 64bits decoding mode is 64. + */ + + if (effAdrSz == Decode64Bits) operands_set_tsi(op, O_SMEM, 64, R_RAX); + else if (effAdrSz == Decode32Bits) { + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + operands_set_tsi(op, O_SMEM, 32, R_EAX); + } else { + ps->usedPrefixes |= INST_PRE_ADDR_SIZE; + operands_set_tsi(op, O_SMEM, 16, R_AX); + } + break; + case OT_VXMM: + operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + vexV); + break; + case OT_XMM_IMM: + ci->codeLen -= sizeof(int8_t); + if (ci->codeLen < 0) return FALSE; + + if (ci->dt == Decode32Bits) reg = (*ci->code >> 4) & 0x7; + else reg = (*ci->code >> 4) & 0xf; + operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg); + + ci->code += sizeof(int8_t); + break; + case OT_YXMM: + if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE; + if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg); + else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg); + break; + case OT_YXMM_IMM: + ci->codeLen -= sizeof(int8_t); + if (ci->codeLen < 0) return FALSE; + + if (ci->dt == Decode32Bits) reg = (*ci->code >> 4) & 0x7; + else reg = (*ci->code >> 4) & 0xf; + + if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg); + else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + reg); + + ci->code += sizeof(int8_t); + break; + case OT_YMM: + if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE; + operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + reg); + break; + case OT_VYMM: + operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + vexV); + break; + case OT_VYXMM: + if (ps->vrex & PREFIX_EX_L) operands_set_tsi(op, O_REG, 256, AVXREGS_BASE + vexV); + else operands_set_tsi(op, O_REG, 128, SSEREGS_BASE + vexV); + break; + case OT_WREG32_64: + if (vrex & PREFIX_EX_R) reg += EX_GPR_BASE; + if (ps->vrex & PREFIX_EX_W) operands_set_tsi(op, O_REG, 64, REGS64_BASE + reg); + else operands_set_tsi(op, O_REG, 32, REGS32_BASE + reg); + break; + default: return FALSE; + } + + if ((op->type == O_REG) || (op->type == O_SMEM) || (op->type == O_MEM)) { + di->usedRegistersMask |= _REGISTERTORCLASS[op->index]; + } + + return TRUE; +} diff --git a/source/distorm/operands.h b/source/distorm/operands.h new file mode 100644 index 0000000..883d59b --- /dev/null +++ b/source/distorm/operands.h @@ -0,0 +1,28 @@ +/* +operands.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef OPERANDS_H +#define OPERANDS_H + +#include "config.h" +#include "decoder.h" +#include "prefix.h" +#include "instructions.h" + + +extern uint32_t _REGISTERTORCLASS[]; + +int operands_extract(_CodeInfo* ci, _DInst* di, _InstInfo* ii, + _iflags instFlags, _OpType type, _OperandNumberType opNum, + unsigned int modrm, _PrefixState* ps, _DecodeType effOpSz, + _DecodeType effAdrSz, int* lockableInstruction); + +#endif /* OPERANDS_H */ diff --git a/source/distorm/prefix.c b/source/distorm/prefix.c new file mode 100644 index 0000000..77cbeea --- /dev/null +++ b/source/distorm/prefix.c @@ -0,0 +1,368 @@ +/* +prefix.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "prefix.h" + +#include "x86defs.h" +#include "instructions.h" +#include "distorm/mnemonics.h" + + +/* + * The main purpose of this module is to keep track of all kind of prefixes a single instruction may have. + * The problem is that a single instruction may have up to six different prefix-types. + * That's why I have to detect such cases and drop those excess prefixes. + */ + +int prefixes_is_valid(unsigned int ch, _DecodeType dt) +{ + switch (ch) { + /* for i in xrange(0x40, 0x50): print "case 0x%2x:" % i */ + case 0x40: /* REX: */ + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: return (dt == Decode64Bits); + case PREFIX_LOCK: return TRUE; + case PREFIX_REPNZ: return TRUE; + case PREFIX_REP: return TRUE; + case PREFIX_CS: return TRUE; + case PREFIX_SS: return TRUE; + case PREFIX_DS: return TRUE; + case PREFIX_ES: return TRUE; + case PREFIX_FS: return TRUE; + case PREFIX_GS: return TRUE; + case PREFIX_OP_SIZE: return TRUE; + case PREFIX_ADDR_SIZE: return TRUE; + /* The VEXs might be false positives, the decode_perfixes will determine for sure. */ + case PREFIX_VEX2b: /* VEX is supported for all modes, because 16 bits Pmode is included. */ + case PREFIX_VEX3b: return TRUE; + } + return FALSE; +} + +/* Ignore a specific prefix type. */ +void prefixes_ignore(_PrefixState* ps, _PrefixIndexer pi) +{ + /* + * If that type of prefix appeared already, set the bit of that *former* prefix. + * Anyway, set the new index of that prefix type to the current index, so next time we know its position. + */ + if (ps->pfxIndexer[pi] != PFXIDX_NONE) ps->unusedPrefixesMask |= (1 << ps->pfxIndexer[pi]); +} + +/* Ignore all prefix. */ +void prefixes_ignore_all(_PrefixState* ps) +{ + int i; + for (i = 0; i < PFXIDX_MAX; i++) + prefixes_ignore(ps, i); +} + +/* Calculates which prefixes weren't used and accordingly sets the bits in the unusedPrefixesMask. */ +uint16_t prefixes_set_unused_mask(_PrefixState* ps) +{ + /* + * The decodedPrefixes represents the prefixes that were *read* from the binary stream for the instruction. + * The usedPrefixes represents the prefixes that were actually used by the instruction in the *decode* phase. + * Xoring between the two will result in a 'diff' which returns the prefixes that were read + * from the stream *and* that were never used in the actual decoding. + * + * Only one prefix per type can be set in decodedPrefixes from the stream. + * Therefore it's enough to check each type once and set the flag accordingly. + * That's why we had to book-keep each prefix type and its position. + * So now we know which bits we need to set exactly in the mask. + */ + _iflags unusedPrefixesDiff = ps->decodedPrefixes ^ ps->usedPrefixes; + + /* Examine unused prefixes by type: */ + /* + * About REX: it might be set in the diff although it was never in the stream itself. + * This is because the vrex is shared between VEX and REX and some places flag it as REX usage, while + * we were really decoding an AVX instruction. + * It's not a big problem, because the prefixes_ignore func will ignore it anyway, + * since it wasn't seen earlier. But it's important to know this. + */ + if (unusedPrefixesDiff & INST_PRE_REX) prefixes_ignore(ps, PFXIDX_REX); + if (unusedPrefixesDiff & INST_PRE_SEGOVRD_MASK) prefixes_ignore(ps, PFXIDX_SEG); + if (unusedPrefixesDiff & INST_PRE_LOKREP_MASK) prefixes_ignore(ps, PFXIDX_LOREP); + if (unusedPrefixesDiff & INST_PRE_OP_SIZE) prefixes_ignore(ps, PFXIDX_OP_SIZE); + if (unusedPrefixesDiff & INST_PRE_ADDR_SIZE) prefixes_ignore(ps, PFXIDX_ADRS); + /* If a VEX instruction was found, its prefix is considered as used, therefore no point for checking for it. */ + + return ps->unusedPrefixesMask; +} + +/* + * Mark a prefix as unused, and bookkeep where we last saw this same type, + * because in the future we might want to disable it too. + */ +_INLINE_ void prefixes_track_unused(_PrefixState* ps, int index, _PrefixIndexer pi) +{ + prefixes_ignore(ps, pi); + /* Book-keep the current index for this type. */ + ps->pfxIndexer[pi] = index; +} + +/* + * Read as many prefixes as possible, up to 15 bytes, and halt when we encounter non-prefix byte. + * This algorithm tries to imitate a real processor, where the same prefix can appear a few times, etc. + * The tiny complexity is that we want to know when a prefix was superfluous and mark any copy of it as unused. + * Note that the last prefix of its type will be considered as used, and all the others (of same type) before it as unused. + */ +void prefixes_decode(const uint8_t* code, int codeLen, _PrefixState* ps, _DecodeType dt) +{ + int index, done; + uint8_t vex; + + /* + * First thing to do, scan for prefixes, there are six types of prefixes. + * There may be up to six prefixes before a single instruction, not the same type, no special order, + * except REX/VEX must precede immediately the first opcode byte. + * BTW - This is the reason why I didn't make the REP prefixes part of the instructions (STOS/SCAS/etc). + * + * Another thing, the instruction maximum size is 15 bytes, thus if we read more than 15 bytes, we will halt. + * + * We attach all prefixes to the next instruction, there might be two or more occurrences from the same prefix. + * Also, since VEX can be allowed only once we will test it separately. + */ + for (index = 0, done = FALSE; + (codeLen > 0) && (code - ps->start < INST_MAXIMUM_SIZE); + code++, codeLen--, index++) { + /* + NOTE: AMD treat lock/rep as two different groups... But I am based on Intel. + + - Lock and Repeat: + - 0xF0 — LOCK + - 0xF2 — REPNE/REPNZ + - 0xF3 - REP/REPE/REPZ + - Segment Override: + - 0x2E - CS + - 0x36 - SS + - 0x3E - DS + - 0x26 - ES + - 0x64 - FS + - 0x65 - GS + - Operand-Size Override: 0x66, switching default size. + - Address-Size Override: 0x67, switching default size. + + 64 Bits: + - REX: 0x40 - 0x4f, extends register access. + - 2 Bytes VEX: 0xc4 + - 3 Bytes VEX: 0xc5 + 32 Bits: + - 2 Bytes VEX: 0xc4 11xx-xxxx + - 3 Bytes VEX: 0xc5 11xx-xxxx + */ + + /* Examine what type of prefix we got. */ + switch (*code) + { + /* REX type, 64 bits decoding mode only: */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + if (dt == Decode64Bits) { + ps->decodedPrefixes |= INST_PRE_REX; + ps->vrex = *code & 0xf; /* Keep only BXRW. */ + ps->rexPos = code; + ps->prefixExtType = PET_REX; + prefixes_track_unused(ps, index, PFXIDX_REX); + } else done = TRUE; /* If we are not in 64 bits mode, it's an instruction, then halt. */ + break; + + /* LOCK and REPx type: */ + case PREFIX_LOCK: + ps->decodedPrefixes |= INST_PRE_LOCK; + prefixes_track_unused(ps, index, PFXIDX_LOREP); + break; + case PREFIX_REPNZ: + ps->decodedPrefixes |= INST_PRE_REPNZ; + prefixes_track_unused(ps, index, PFXIDX_LOREP); + break; + case PREFIX_REP: + ps->decodedPrefixes |= INST_PRE_REP; + prefixes_track_unused(ps, index, PFXIDX_LOREP); + break; + + /* Seg Overide type: */ + case PREFIX_CS: + ps->decodedPrefixes |= INST_PRE_CS; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + case PREFIX_SS: + ps->decodedPrefixes |= INST_PRE_SS; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + case PREFIX_DS: + ps->decodedPrefixes |= INST_PRE_DS; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + case PREFIX_ES: + ps->decodedPrefixes |= INST_PRE_ES; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + case PREFIX_FS: + ps->decodedPrefixes |= INST_PRE_FS; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + case PREFIX_GS: + ps->decodedPrefixes |= INST_PRE_GS; + prefixes_track_unused(ps, index, PFXIDX_SEG); + break; + + /* Op Size type: */ + case PREFIX_OP_SIZE: + ps->decodedPrefixes |= INST_PRE_OP_SIZE; + prefixes_track_unused(ps, index, PFXIDX_OP_SIZE); + break; + + /* Addr Size type: */ + case PREFIX_ADDR_SIZE: + ps->decodedPrefixes |= INST_PRE_ADDR_SIZE; + prefixes_track_unused(ps, index, PFXIDX_ADRS); + break; + + /* Non-prefix byte now, so break 2. */ + default: done = TRUE; break; + } + if (done) break; + } + + /* 2 Bytes VEX: */ + if ((codeLen >= 2) && + (*code == PREFIX_VEX2b) && + ((code - ps->start) <= INST_MAXIMUM_SIZE - 2)) { + /* + * In 32 bits the second byte has to be in the special range of Mod=11. + * Otherwise it might be a normal LDS instruction. + */ + if ((dt == Decode64Bits) || (*(code + 1) >= INST_DIVIDED_MODRM)) { + ps->vexPos = code + 1; + ps->decodedPrefixes |= INST_PRE_VEX; + ps->prefixExtType = PET_VEX2BYTES; + + /* + * VEX 1 byte bits: + * |7-6--3-2-10| + * |R|vvvv|L|pp| + * |-----------| + */ + + /* -- Convert from VEX prefix to VREX flags -- */ + vex = *ps->vexPos; + if (~vex & 0x80 && dt == Decode64Bits) ps->vrex |= PREFIX_EX_R; /* Convert VEX.R. */ + if (vex & 4) ps->vrex |= PREFIX_EX_L; /* Convert VEX.L. */ + + code += 2; + } + } + + /* 3 Bytes VEX: */ + if ((codeLen >= 3) && + (*code == PREFIX_VEX3b) && + ((code - ps->start) <= INST_MAXIMUM_SIZE - 3) && + (~ps->decodedPrefixes & INST_PRE_VEX)) { + /* + * In 32 bits the second byte has to be in the special range of Mod=11. + * Otherwise it might be a normal LES instruction. + * And we don't care now about the 3rd byte. + */ + if ((dt == Decode64Bits) || (*(code + 1) >= INST_DIVIDED_MODRM)) { + ps->vexPos = code + 1; + ps->decodedPrefixes |= INST_PRE_VEX; + ps->prefixExtType = PET_VEX3BYTES; + + /* + * VEX first and second bytes: + * |7-6-5-4----0| |7-6--3-2-10| + * |R|X|B|m-mmmm| |W|vvvv|L|pp| + * |------------| |-----------| + */ + + /* -- Convert from VEX prefix to VREX flags -- */ + vex = *ps->vexPos; + ps->vrex |= ((~vex >> 5) & 0x7); /* Shift and invert VEX.R/X/B to their place */ + vex = *(ps->vexPos + 1); + if (vex & 4) ps->vrex |= PREFIX_EX_L; /* Convert VEX.L. */ + if (vex & 0x80) ps->vrex |= PREFIX_EX_W; /* Convert VEX.W. */ + + /* Clear some flags if the mode isn't 64 bits. */ + if (dt != Decode64Bits) ps->vrex &= ~(PREFIX_EX_B | PREFIX_EX_X | PREFIX_EX_R | PREFIX_EX_W); + + code += 3; + } + } + + /* + * Save last byte scanned address, so the decoder could keep on scanning from this point and on and on and on. + * In addition the decoder is able to know that the last byte could lead to MMX/SSE instructions (preceding REX if exists). + */ + ps->last = code; /* ps->last points to an opcode byte. */ +} + +/* + * For every memory-indirection operand we want to set its corresponding default segment. + * If the segment is being overrided, we need to see whether we use it or not. + * We will use it only if it's not the default one already. + */ +void prefixes_use_segment(_iflags defaultSeg, _PrefixState* ps, _DecodeType dt, _DInst* di) +{ + _iflags flags = 0; + if (dt == Decode64Bits) flags = ps->decodedPrefixes & INST_PRE_SEGOVRD_MASK64; + else flags = ps->decodedPrefixes & INST_PRE_SEGOVRD_MASK; + + if ((flags == 0) || (flags == defaultSeg)) { + flags = defaultSeg; + di->segment |= SEGMENT_DEFAULT; + } else if (flags != defaultSeg) { + /* Use it only if it's non-default segment. */ + ps->usedPrefixes |= flags; + } + + /* ASSERT: R_XX must be below 128. */ + switch (flags) + { + case INST_PRE_ES: di->segment |= R_ES; break; + case INST_PRE_CS: di->segment |= R_CS; break; + case INST_PRE_SS: di->segment |= R_SS; break; + case INST_PRE_DS: di->segment |= R_DS; break; + case INST_PRE_FS: di->segment |= R_FS; break; + case INST_PRE_GS: di->segment |= R_GS; break; + } + + /* If it's one of the CS,SS,DS,ES and the mode is 64 bits, set segment it to none, since it's ignored. */ + if ((dt == Decode64Bits) && (flags & INST_PRE_SEGOVRD_MASK32)) di->segment = R_NONE; +} diff --git a/source/distorm/prefix.h b/source/distorm/prefix.h new file mode 100644 index 0000000..f1f53c4 --- /dev/null +++ b/source/distorm/prefix.h @@ -0,0 +1,64 @@ +/* +prefix.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef PREFIX_H +#define PREFIX_H + +#include "config.h" +#include "decoder.h" + + +/* Specifies the type of the extension prefix, such as: REX, 2 bytes VEX, 3 bytes VEX. */ +typedef enum {PET_NONE = 0, PET_REX, PET_VEX2BYTES, PET_VEX3BYTES} _PrefixExtType; + +/* Specifies an index into a table of prefixes by their type. */ +typedef enum {PFXIDX_NONE = -1, PFXIDX_REX, PFXIDX_LOREP, PFXIDX_SEG, PFXIDX_OP_SIZE, PFXIDX_ADRS, PFXIDX_MAX} _PrefixIndexer; + +/* +* This holds the prefixes state for the current instruction we decode. +* decodedPrefixes includes all specific prefixes that the instruction got. +* start is a pointer to the first prefix to take into account. +* last is a pointer to the last byte we scanned. +* Other pointers are used to keep track of prefixes positions and help us know if they appeared already and where. +*/ +typedef struct { + _iflags decodedPrefixes, usedPrefixes; + const uint8_t *start, *last, *vexPos, *rexPos; + _PrefixExtType prefixExtType; + uint16_t unusedPrefixesMask; + /* Indicates whether the operand size prefix (0x66) was used as a mandatory prefix. */ + int isOpSizeMandatory; + /* If VEX prefix is used, store the VEX.vvvv field. */ + unsigned int vexV; + /* The fields B/X/R/W/L of REX and VEX are stored together in this byte. */ + unsigned int vrex; + + /* !! Make sure pfxIndexer is LAST! Otherwise memset won't work well with it. !! */ + + /* Holds the offset to the prefix byte by its type. */ + int pfxIndexer[PFXIDX_MAX]; +} _PrefixState; + +/* +* Intel supports 6 types of prefixes, whereas AMD supports 5 types (lock is seperated from rep/nz). +* REX is the fifth prefix type, this time I'm based on AMD64. +* VEX is the 6th, though it can't be repeated. +*/ +#define MAX_PREFIXES (5) + +int prefixes_is_valid(unsigned int ch, _DecodeType dt); +void prefixes_ignore(_PrefixState* ps, _PrefixIndexer pi); +void prefixes_ignore_all(_PrefixState* ps); +uint16_t prefixes_set_unused_mask(_PrefixState* ps); +void prefixes_decode(const uint8_t* code, int codeLen, _PrefixState* ps, _DecodeType dt); +void prefixes_use_segment(_iflags defaultSeg, _PrefixState* ps, _DecodeType dt, _DInst* di); + +#endif /* PREFIX_H */ diff --git a/source/distorm/textdefs.c b/source/distorm/textdefs.c new file mode 100644 index 0000000..84b5a05 --- /dev/null +++ b/source/distorm/textdefs.c @@ -0,0 +1,173 @@ +/* +textdefs.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "textdefs.h" +#include "compat.h" + +#ifndef DISTORM_LIGHT + +static uint8_t Nibble2ChrTable[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'}; +#define NIBBLE_TO_CHR Nibble2ChrTable[t] + +void _FASTCALL_ str_hex_b(_WString* s, unsigned int x) +{ + /* + * def prebuilt(): + * s = "" + * for i in xrange(256): + * if ((i % 0x10) == 0): + * s += "\r\n" + * s += "\"%02x\", " % (i) + * return s + */ + static int8_t TextBTable[256][3] = { + "00", "01", "02", "03", "04", "05", "06", "07", "08", "09", "0a", "0b", "0c", "0d", "0e", "0f", + "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "1a", "1b", "1c", "1d", "1e", "1f", + "20", "21", "22", "23", "24", "25", "26", "27", "28", "29", "2a", "2b", "2c", "2d", "2e", "2f", + "30", "31", "32", "33", "34", "35", "36", "37", "38", "39", "3a", "3b", "3c", "3d", "3e", "3f", + "40", "41", "42", "43", "44", "45", "46", "47", "48", "49", "4a", "4b", "4c", "4d", "4e", "4f", + "50", "51", "52", "53", "54", "55", "56", "57", "58", "59", "5a", "5b", "5c", "5d", "5e", "5f", + "60", "61", "62", "63", "64", "65", "66", "67", "68", "69", "6a", "6b", "6c", "6d", "6e", "6f", + "70", "71", "72", "73", "74", "75", "76", "77", "78", "79", "7a", "7b", "7c", "7d", "7e", "7f", + "80", "81", "82", "83", "84", "85", "86", "87", "88", "89", "8a", "8b", "8c", "8d", "8e", "8f", + "90", "91", "92", "93", "94", "95", "96", "97", "98", "99", "9a", "9b", "9c", "9d", "9e", "9f", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "aa", "ab", "ac", "ad", "ae", "af", + "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", "b8", "b9", "ba", "bb", "bc", "bd", "be", "bf", + "c0", "c1", "c2", "c3", "c4", "c5", "c6", "c7", "c8", "c9", "ca", "cb", "cc", "cd", "ce", "cf", + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "da", "db", "dc", "dd", "de", "df", + "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "e8", "e9", "ea", "eb", "ec", "ed", "ee", "ef", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "fa", "fb", "fc", "fd", "fe", "ff" + }; + + /* + * Fixed length of 3 including null terminate character. + */ + COMPAT(memcpy)(&s->p[s->length], TextBTable[x & 255], 3); + s->length += 2; +} + +void _FASTCALL_ str_code_hb(_WString* s, unsigned int x) +{ + static int8_t TextHBTable[256][5] = { + /* + * def prebuilt(): + * s = "" + * for i in xrange(256): + * if ((i % 0x10) == 0): + * s += "\r\n" + * s += "\"0x%x\", " % (i) + * return s + */ + "0x0", "0x1", "0x2", "0x3", "0x4", "0x5", "0x6", "0x7", "0x8", "0x9", "0xa", "0xb", "0xc", "0xd", "0xe", "0xf", + "0x10", "0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18", "0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f", + "0x20", "0x21", "0x22", "0x23", "0x24", "0x25", "0x26", "0x27", "0x28", "0x29", "0x2a", "0x2b", "0x2c", "0x2d", "0x2e", "0x2f", + "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "0x3f", + "0x40", "0x41", "0x42", "0x43", "0x44", "0x45", "0x46", "0x47", "0x48", "0x49", "0x4a", "0x4b", "0x4c", "0x4d", "0x4e", "0x4f", + "0x50", "0x51", "0x52", "0x53", "0x54", "0x55", "0x56", "0x57", "0x58", "0x59", "0x5a", "0x5b", "0x5c", "0x5d", "0x5e", "0x5f", + "0x60", "0x61", "0x62", "0x63", "0x64", "0x65", "0x66", "0x67", "0x68", "0x69", "0x6a", "0x6b", "0x6c", "0x6d", "0x6e", "0x6f", + "0x70", "0x71", "0x72", "0x73", "0x74", "0x75", "0x76", "0x77", "0x78", "0x79", "0x7a", "0x7b", "0x7c", "0x7d", "0x7e", "0x7f", + "0x80", "0x81", "0x82", "0x83", "0x84", "0x85", "0x86", "0x87", "0x88", "0x89", "0x8a", "0x8b", "0x8c", "0x8d", "0x8e", "0x8f", + "0x90", "0x91", "0x92", "0x93", "0x94", "0x95", "0x96", "0x97", "0x98", "0x99", "0x9a", "0x9b", "0x9c", "0x9d", "0x9e", "0x9f", + "0xa0", "0xa1", "0xa2", "0xa3", "0xa4", "0xa5", "0xa6", "0xa7", "0xa8", "0xa9", "0xaa", "0xab", "0xac", "0xad", "0xae", "0xaf", + "0xb0", "0xb1", "0xb2", "0xb3", "0xb4", "0xb5", "0xb6", "0xb7", "0xb8", "0xb9", "0xba", "0xbb", "0xbc", "0xbd", "0xbe", "0xbf", + "0xc0", "0xc1", "0xc2", "0xc3", "0xc4", "0xc5", "0xc6", "0xc7", "0xc8", "0xc9", "0xca", "0xcb", "0xcc", "0xcd", "0xce", "0xcf", + "0xd0", "0xd1", "0xd2", "0xd3", "0xd4", "0xd5", "0xd6", "0xd7", "0xd8", "0xd9", "0xda", "0xdb", "0xdc", "0xdd", "0xde", "0xdf", + "0xe0", "0xe1", "0xe2", "0xe3", "0xe4", "0xe5", "0xe6", "0xe7", "0xe8", "0xe9", "0xea", "0xeb", "0xec", "0xed", "0xee", "0xef", + "0xf0", "0xf1", "0xf2", "0xf3", "0xf4", "0xf5", "0xf6", "0xf7", "0xf8", "0xf9", "0xfa", "0xfb", "0xfc", "0xfd", "0xfe", "0xff" + }; + + if (x < 0x10) { /* < 0x10 has a fixed length of 4 including null terminate. */ + memcpy(&s->p[s->length], TextHBTable[x & 255], 4); + s->length += 3; + } else { /* >= 0x10 has a fixed length of 5 including null terminate. */ + memcpy(&s->p[s->length], TextHBTable[x & 255], 5); + s->length += 4; + } +} + +void _FASTCALL_ str_code_hdw(_WString* s, uint32_t x) +{ + int8_t* buf; + int i = 0, shift = 0; + unsigned int t = 0; + + buf = (int8_t*)&s->p[s->length]; + + buf[0] = '0'; + buf[1] = 'x'; + buf += 2; + + for (shift = 28; shift != 0; shift -= 4) { + t = (x >> shift) & 0xf; + if (i | t) buf[i++] = NIBBLE_TO_CHR; + } + t = x & 0xf; + buf[i++] = NIBBLE_TO_CHR; + + s->length += i + 2; + buf[i] = '\0'; +} + +void _FASTCALL_ str_code_hqw(_WString* s, uint8_t src[8]) +{ + int8_t* buf; + int i = 0, shift = 0; + uint32_t x = RULONG(&src[sizeof(int32_t)]); + int t; + + buf = (int8_t*)&s->p[s->length]; + buf[0] = '0'; + buf[1] = 'x'; + buf += 2; + + for (shift = 28; shift != -4; shift -= 4) { + t = (x >> shift) & 0xf; + if (i | t) buf[i++] = NIBBLE_TO_CHR; + } + + x = RULONG(src); + for (shift = 28; shift != 0; shift -= 4) { + t = (x >> shift) & 0xf; + if (i | t) buf[i++] = NIBBLE_TO_CHR; + } + t = x & 0xf; + buf[i++] = NIBBLE_TO_CHR; + + s->length += i + 2; + buf[i] = '\0'; +} + +#ifdef SUPPORT_64BIT_OFFSET +void _FASTCALL_ str_off64(_WString* s, OFFSET_INTEGER x) +{ + int8_t* buf; + int i = 0, shift = 0; + OFFSET_INTEGER t = 0; + + buf = (int8_t*)&s->p[s->length]; + + buf[0] = '0'; + buf[1] = 'x'; + buf += 2; + + for (shift = 60; shift != 0; shift -= 4) { + t = (x >> shift) & 0xf; + if (i | t) buf[i++] = NIBBLE_TO_CHR; + } + t = x & 0xf; + buf[i++] = NIBBLE_TO_CHR; + + s->length += i + 2; + buf[i] = '\0'; +} +#endif /* SUPPORT_64BIT_OFFSET */ + +#endif /* DISTORM_LIGHT */ diff --git a/source/distorm/textdefs.h b/source/distorm/textdefs.h new file mode 100644 index 0000000..05cf8d7 --- /dev/null +++ b/source/distorm/textdefs.h @@ -0,0 +1,57 @@ +/* +textdefs.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef TEXTDEFS_H +#define TEXTDEFS_H + +#include "config.h" +#include "wstring.h" + +#ifndef DISTORM_LIGHT + +#define PLUS_DISP_CHR '+' +#define MINUS_DISP_CHR '-' +#define OPEN_CHR '[' +#define CLOSE_CHR ']' +#define SP_CHR ' ' +#define SEG_OFF_CHR ':' + +/* +Naming Convention: + +* get - returns a pointer to a string. +* str - concatenates to string. + +* hex - means the function is used for hex dump (number is padded to required size) - Little Endian output. +* code - means the function is used for disassembled instruction - Big Endian output. +* off - means the function is used for 64bit offset - Big Endian output. + +* h - '0x' in front of the string. + +* b - byte +* dw - double word (can be used for word also) +* qw - quad word + +* all numbers are in HEX. +*/ + +void _FASTCALL_ str_hex_b(_WString* s, unsigned int x); +void _FASTCALL_ str_code_hb(_WString* s, unsigned int x); +void _FASTCALL_ str_code_hdw(_WString* s, uint32_t x); +void _FASTCALL_ str_code_hqw(_WString* s, uint8_t src[8]); + +#ifdef SUPPORT_64BIT_OFFSET +void _FASTCALL_ str_off64(_WString* s, OFFSET_INTEGER x); +#endif + +#endif /* DISTORM_LIGHT */ + +#endif /* TEXTDEFS_H */ diff --git a/source/distorm/wstring.c b/source/distorm/wstring.c new file mode 100644 index 0000000..ee858be --- /dev/null +++ b/source/distorm/wstring.c @@ -0,0 +1,48 @@ +/* +wstring.c + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#include "wstring.h" +#include "compat.h" + +#ifndef DISTORM_LIGHT + +void strclear_WS(_WString* s) +{ + s->p[0] = '\0'; + s->length = 0; +} + +void chrcat_WS(_WString* s, uint8_t ch) +{ + s->p[s->length] = ch; + s->p[s->length + 1] = '\0'; + s->length += 1; +} + +void strcpylen_WS(_WString* s, const int8_t* buf, unsigned int len) +{ + s->length = len; + COMPAT(memcpy)((int8_t*)s->p, buf, len + 1); +} + +void strcatlen_WS(_WString* s, const int8_t* buf, unsigned int len) +{ + COMPAT(memcpy)((int8_t*)&s->p[s->length], buf, len + 1); + s->length += len; +} + +void strcat_WS(_WString* s, const _WString* s2) +{ + COMPAT(memcpy)((int8_t*)&s->p[s->length], s2->p, s2->length + 1); + s->length += s2->length; +} + +#endif /* DISTORM_LIGHT */ diff --git a/source/distorm/wstring.h b/source/distorm/wstring.h new file mode 100644 index 0000000..1dbaa2f --- /dev/null +++ b/source/distorm/wstring.h @@ -0,0 +1,35 @@ +/* +wstring.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef WSTRING_H +#define WSTRING_H + +#include "config.h" + +#ifndef DISTORM_LIGHT + +void strclear_WS(_WString* s); +void chrcat_WS(_WString* s, uint8_t ch); +void strcpylen_WS(_WString* s, const int8_t* buf, unsigned int len); +void strcatlen_WS(_WString* s, const int8_t* buf, unsigned int len); +void strcat_WS(_WString* s, const _WString* s2); + +/* +* Warning, this macro should be used only when the compiler knows the size of string in advance! +* This macro is used in order to spare the call to strlen when the strings are known already. +* Note: sizeof includes NULL terminated character. +*/ +#define strcat_WSN(s, t) strcatlen_WS((s), ((const int8_t*)t), sizeof((t))-1) +#define strcpy_WSN(s, t) strcpylen_WS((s), ((const int8_t*)t), sizeof((t))-1) + +#endif /* DISTORM_LIGHT */ + +#endif /* WSTRING_H */ diff --git a/source/distorm/x86defs.h b/source/distorm/x86defs.h new file mode 100644 index 0000000..36fea6d --- /dev/null +++ b/source/distorm/x86defs.h @@ -0,0 +1,82 @@ +/* +x86defs.h + +diStorm3 - Powerful disassembler for X86/AMD64 +http://ragestorm.net/distorm/ +distorm at gmail dot com +Copyright (C) 2003-2016 Gil Dabah +This library is licensed under the BSD license. See the file COPYING. +*/ + + +#ifndef X86DEFS_H +#define X86DEFS_H + + +#define SEG_REGS_MAX (6) +#define CREGS_MAX (9) +#define DREGS_MAX (8) + +/* Maximum instruction size, including prefixes */ +#define INST_MAXIMUM_SIZE (15) + +/* Maximum range of imm8 (comparison type) of special SSE CMP instructions. */ +#define INST_CMP_MAX_RANGE (8) + +/* Maximum range of imm8 (comparison type) of special AVX VCMP instructions. */ +#define INST_VCMP_MAX_RANGE (32) + +/* Wait instruction byte code. */ +#define INST_WAIT_INDEX (0x9b) + +/* Lea instruction byte code. */ +#define INST_LEA_INDEX (0x8d) + +/* NOP/XCHG instruction byte code. */ +#define INST_NOP_INDEX (0x90) + +/* ARPL/MOVSXD instruction byte code. */ +#define INST_ARPL_INDEX (0x63) + +/* + * Minimal MODR/M value of divided instructions. + * It's 0xc0, two MSBs set, which indicates a general purpose register is used too. + */ +#define INST_DIVIDED_MODRM (0xc0) + +/* This is the escape byte value used for 3DNow! instructions. */ +#define _3DNOW_ESCAPE_BYTE (0x0f) + +#define PREFIX_LOCK (0xf0) +#define PREFIX_REPNZ (0xf2) +#define PREFIX_REP (0xf3) +#define PREFIX_CS (0x2e) +#define PREFIX_SS (0x36) +#define PREFIX_DS (0x3e) +#define PREFIX_ES (0x26) +#define PREFIX_FS (0x64) +#define PREFIX_GS (0x65) +#define PREFIX_OP_SIZE (0x66) +#define PREFIX_ADDR_SIZE (0x67) +#define PREFIX_VEX2b (0xc5) +#define PREFIX_VEX3b (0xc4) + +/* REX prefix value range, 64 bits mode decoding only. */ +#define PREFIX_REX_LOW (0x40) +#define PREFIX_REX_HI (0x4f) +/* In order to use the extended GPR's we have to add 8 to the Modr/M info values. */ +#define EX_GPR_BASE (8) + +/* Mask for REX and VEX features: */ +/* Base */ +#define PREFIX_EX_B (1) +/* Index */ +#define PREFIX_EX_X (2) +/* Register */ +#define PREFIX_EX_R (4) +/* Operand Width */ +#define PREFIX_EX_W (8) +/* Vector Lengh */ +#define PREFIX_EX_L (0x10) + +#endif /* X86DEFS_H */ |