1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
|
#include <dt-bindings/net/qcom-ipq-ess.h>
&soc {
bias_pll_cc_clk: bias-pll-cc-clk {
compatible = "fixed-clock";
clock-frequency = <300000000>;
clock-output-names = "bias_pll_cc_clk";
#clock-cells = <0>;
};
bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
compatible = "fixed-clock";
clock-frequency = <416500000>;
clock-output-names = "bias_pll_nss_noc_clk";
#clock-cells = <0>;
};
edma: edma@3ab00000 {
compatible = "qcom,edma";
reg = <0x0 0x3ab00000 0x0 0xabe00>;
reg-names = "edma-reg-base";
qcom,txdesc-ring-start = <23>;
qcom,txdesc-rings = <1>;
qcom,txcmpl-ring-start = <23>;
qcom,txcmpl-rings = <1>;
qcom,rxfill-ring-start = <7>;
qcom,rxfill-rings = <1>;
qcom,rxdesc-ring-start = <15>;
qcom,rxdesc-rings = <1>;
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
resets = <&gcc GCC_EDMA_HW_RESET>;
reset-names = "edma_rst";
status = "disabled";
};
ess_instance: ess-instance {
#address-cells = <1>;
#size-cells = <1>;
num_devices = <1>;
switch: ess-switch@3a000000 {
compatible = "qcom,ess-switch-ipq60xx";
reg = <0x3a000000 0x1000000>;
switch_access_mode = "local bus";
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
<&gcc GCC_UNIPHY0_SYS_CLK>,
<&gcc GCC_UNIPHY1_AHB_CLK>,
<&gcc GCC_UNIPHY1_SYS_CLK>,
<&gcc GCC_PORT1_MAC_CLK>,
<&gcc GCC_PORT2_MAC_CLK>,
<&gcc GCC_PORT3_MAC_CLK>,
<&gcc GCC_PORT4_MAC_CLK>,
<&gcc GCC_PORT5_MAC_CLK>,
<&gcc GCC_NSS_PPE_CLK>,
<&gcc GCC_NSS_PPE_CFG_CLK>,
<&gcc GCC_NSSNOC_PPE_CLK>,
<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
<&gcc GCC_NSS_EDMA_CLK>,
<&gcc GCC_NSS_EDMA_CFG_CLK>,
<&gcc GCC_NSS_PPE_IPE_CLK>,
<&gcc GCC_MDIO_AHB_CLK>,
<&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_PORT1_RX_CLK>,
<&gcc GCC_NSS_PORT1_TX_CLK>,
<&gcc GCC_NSS_PORT2_RX_CLK>,
<&gcc GCC_NSS_PORT2_TX_CLK>,
<&gcc GCC_NSS_PORT3_RX_CLK>,
<&gcc GCC_NSS_PORT3_TX_CLK>,
<&gcc GCC_NSS_PORT4_RX_CLK>,
<&gcc GCC_NSS_PORT4_TX_CLK>,
<&gcc GCC_NSS_PORT5_RX_CLK>,
<&gcc GCC_NSS_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
<&gcc NSS_PORT5_RX_CLK_SRC>,
<&gcc NSS_PORT5_TX_CLK_SRC>,
<&gcc GCC_SNOC_NSSNOC_CLK>;
clock-names = "cmn_ahb_clk", "cmn_sys_clk",
"uniphy0_ahb_clk", "uniphy0_sys_clk",
"uniphy1_ahb_clk", "uniphy1_sys_clk",
"port1_mac_clk", "port2_mac_clk",
"port3_mac_clk", "port4_mac_clk",
"port5_mac_clk",
"nss_ppe_clk", "nss_ppe_cfg_clk",
"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
"nss_edma_clk", "nss_edma_cfg_clk",
"nss_ppe_ipe_clk",
"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
"gcc_nssnoc_snoc_clk",
"gcc_nss_crypto_clk",
"gcc_nss_ptp_ref_clk",
"nss_port1_rx_clk", "nss_port1_tx_clk",
"nss_port2_rx_clk", "nss_port2_tx_clk",
"nss_port3_rx_clk", "nss_port3_tx_clk",
"nss_port4_rx_clk", "nss_port4_tx_clk",
"nss_port5_rx_clk", "nss_port5_tx_clk",
"uniphy0_port1_rx_clk",
"uniphy0_port1_tx_clk",
"uniphy0_port2_rx_clk",
"uniphy0_port2_tx_clk",
"uniphy0_port3_rx_clk",
"uniphy0_port3_tx_clk",
"uniphy0_port4_rx_clk",
"uniphy0_port4_tx_clk",
"uniphy0_port5_rx_clk",
"uniphy0_port5_tx_clk",
"uniphy1_port5_rx_clk",
"uniphy1_port5_tx_clk",
"nss_port5_rx_clk_src",
"nss_port5_tx_clk_src",
"gcc_snoc_nssnoc_clk";
resets = <&gcc GCC_PPE_FULL_RESET>,
<&gcc GCC_UNIPHY0_SOFT_RESET>,
<&gcc GCC_UNIPHY0_XPCS_RESET>,
<&gcc GCC_UNIPHY1_SOFT_RESET>,
<&gcc GCC_UNIPHY1_XPCS_RESET>,
<&gcc GCC_NSSPORT1_RESET>,
<&gcc GCC_NSSPORT2_RESET>,
<&gcc GCC_NSSPORT3_RESET>,
<&gcc GCC_NSSPORT4_RESET>,
<&gcc GCC_NSSPORT5_RESET>,
<&gcc GCC_UNIPHY0_PORT1_ARES>,
<&gcc GCC_UNIPHY0_PORT2_ARES>,
<&gcc GCC_UNIPHY0_PORT3_ARES>,
<&gcc GCC_UNIPHY0_PORT4_ARES>,
<&gcc GCC_UNIPHY0_PORT5_ARES>,
<&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
<&gcc GCC_UNIPHY0_PORT_4_RESET>;
reset-names = "ppe_rst", "uniphy0_soft_rst",
"uniphy0_xpcs_rst", "uniphy1_soft_rst",
"uniphy1_xpcs_rst", "nss_port1_rst",
"nss_port2_rst", "nss_port3_rst",
"nss_port4_rst", "nss_port5_rst",
"uniphy0_port1_dis",
"uniphy0_port2_dis",
"uniphy0_port3_dis",
"uniphy0_port4_dis",
"uniphy0_port5_dis",
"uniphy0_port_4_5_rst",
"uniphy0_port_4_rst";
mdio-bus = <&mdio>;
switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/
switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
status = "disabled";
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpricdrrepriedrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
ess-uniphy@7a00000 {
compatible = "qcom,ess-uniphy";
reg = <0x7a00000 0x30000>;
uniphy_access_mode = "local bus";
};
};
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x0 0x3a001000 0x0 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "psgmii";
status = "disabled";
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x0 0x3a001200 0x0 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "psgmii";
status = "disabled";
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x0 0x3a001400 0x0 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "psgmii";
status = "disabled";
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x0 0x3a001600 0x0 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "psgmii";
status = "disabled";
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x0 0x3a001800 0x0 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "psgmii";
status = "disabled";
};
};
|