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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/include/ "octeon_3xxx.dtsi"
/ {
compatible = "cisco,vedge1000", "cavium,cn6130";
model = "Cisco/Viptela vEdge 1000";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&ciu>;
soc@0 {
smi0: mdio@1180000001800 {
mgmtphy: ethernet-phy@0 {
reg = <0x00>;
};
};
mgmt0: ethernet@1070000100000 {
compatible = "cavium,octeon-5750-mix";
reg = <0x10700 0x100000 0x00 0x100>,
<0x11800 0xe0000000 0x00 0x300>,
<0x11800 0xe0000400 0x00 0x400>,
<0x11800 0xe0002000 0x00 0x08>;
cell-index = <0x00>;
interrupts = <0x00 0x3e 0x01 0x2e>;
nvmem-cells = <&macaddr_eeprom 0>;
nvmem-cell-names = "mac-address";
phy-handle = <&mgmtphy>;
};
pip: pip@11800a0000000 {
interface@0 {
ethernet@0 {
nvmem-cells = <&macaddr_eeprom 3>;
nvmem-cell-names = "mac-address";
label = "lan2";
/delete-property/ local-mac-address;
};
ethernet@1 {
nvmem-cells = <&macaddr_eeprom 4>;
nvmem-cell-names = "mac-address";
label = "lan3";
/delete-property/ local-mac-address;
};
ethernet@2 {
nvmem-cells = <&macaddr_eeprom 1>;
nvmem-cell-names = "mac-address";
label = "lan0";
/delete-property/ local-mac-address;
};
ethernet@3 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x3>;
nvmem-cells = <&macaddr_eeprom 2>;
nvmem-cell-names = "mac-address";
label = "lan1";
};
};
interface@1 {
ethernet@0 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>;
nvmem-cells = <&macaddr_eeprom 7>;
nvmem-cell-names = "mac-address";
label = "lan6";
};
ethernet@1 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x1>;
nvmem-cells = <&macaddr_eeprom 8>;
nvmem-cell-names = "mac-address";
label = "lan7";
};
ethernet@2 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x2>;
nvmem-cells = <&macaddr_eeprom 5>;
nvmem-cell-names = "mac-address";
label = "lan4";
};
ethernet@3 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x3>;
nvmem-cells = <&macaddr_eeprom 6>;
nvmem-cell-names = "mac-address";
label = "lan5";
};
};
};
twsi0: i2c@1180000001000 {
clock-frequency = <400000>;
jc42@18 {
compatible = "jedec,jc-42.4-temp";
reg = <0x18>;
};
};
twsi2: i2c@1180000001200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cavium,octeon-3860-twsi";
reg = <0x11800 0x1200 0x00 0x200>;
interrupts = <0x00 0x3b>;
clock-frequency = <400000>;
tmp@4c {
compatible = "maxim,max6699";
reg = <0x4c>;
};
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
};
tlv-eeprom@54 {
compatible = "atmel,24c512";
reg = <0x54>;
pagesize = <0x80>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_eeprom: mac-address@8 {
compatible = "mac-base";
reg = <0x8 6>;
#nvmem-cell-cells = <1>;
};
};
};
};
uart0: serial@1180000000800 {
clock-frequency = <600000000>;
current-speed = <115200>;
};
uart1: serial@1180000000c00 {
compatible = "cavium,octeon-3860-uart", "ns16550";
reg = <0x11800 0xc00 0x00 0x400>;
reg-shift = <0x03>;
interrupts = <0x00 0x23>;
clock-frequency = <600000000>;
current-speed = <115200>;
};
mmc0: mmc@1180000002000 {
compatible = "cavium,octeon-6130-mmc";
reg = <0x11800 0x2000 0x00 0x100 0x11800 0x168 0x00 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x01 0x13 0x00 0x3f>;
mmc-slot@0 {
compatible = "cavium,octeon-6130-mmc-slot";
reg = <0x00>;
voltage-ranges = <0xce4 0xce4>;
max-frequency = <0x3197500>;
wp-gpios = <&gpio 0x02 0x00>;
cd-gpios = <&gpio 0x03 0x01>;
cavium,bus-max-width = <0x04>;
};
};
bootbus: bootbus@1180000000000 {
compatible = "cavium,octeon-3860-bootbus";
reg = <0x11800 0x00 0x00 0x200>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x00 0x1ec00000 0x1400000>,
<1 0 0x10000 0x20000000 0x00>,
<2 0 0x10000 0x30000000 0x00>,
<3 0 0x10000 0x40000000 0x00>,
<4 0 0x10000 0x50000000 0x00>,
<5 0 0x10000 0x60000000 0x00>,
<6 0 0x00 0x1e000000 0x10000>,
<7 0 0x10000 0x80000000 0x00>;
cavium,cs-config@0 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <0x00>;
cavium,t-adr = <0x0a>;
cavium,t-ce = <0x32>;
cavium,t-oe = <0x32>;
cavium,t-we = <0x23>;
cavium,t-rd-hld = <0x19>;
cavium,t-wr-hld = <0x23>;
cavium,t-pause = <0x00>;
cavium,t-wait = <0x12c>;
cavium,t-page = <0x19>;
cavium,t-rd-dly = <0x00>;
cavium,t-ale = <0x03>;
cavium,pages = <0x00>;
cavium,bus-width = <0x10>;
};
/delete-node/ cavium,cs-config@1;
/delete-node/ cavium,cs-config@2;
/delete-node/ cavium,cs-config@3;
/delete-node/ cavium,cs-config@4;
/delete-node/ cavium,cs-config@5;
cavium,cs-config@6 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <0x06>;
cavium,t-adr = <0x0a>;
cavium,t-ce = <0x0a>;
cavium,t-oe = <0xa0>;
cavium,t-we = <0x64>;
cavium,t-rd-hld = <0x00>;
cavium,t-wr-hld = <0x00>;
cavium,t-pause = <0x32>;
cavium,t-wait = <0x12c>;
cavium,t-page = <0x12c>;
cavium,t-rd-dly = <0x0a>;
cavium,t-ale = <0x3f>;
cavium,pages = <0x00>;
cavium,bus-width = <0x08>;
/delete-property/ cavium,wait-mode;
};
flash0: nor@0,0 {
compatible = "cfi-flash";
reg = <0x00 0x00 0x1000000>;
bank-width = <2>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x00 0x200000>;
read-only;
};
partition@fe0000 {
label = "environment";
reg = <0xfe0000 0x20000>;
};
};
cpld: cpld@6,0 {
compatible = "cisco,n821-cpld", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg-io-width = <1>; // Syscon uses 4-byte accesses by default
reg = <0x06 0x00 0x28>; // This is the regmap to be defined for syscon devices..
ranges = <0 0x06 0x0 0x50>; // .. and this is the addresses to map general subdevices on
};
};
uctl@118006f000000 {
compatible = "cavium,octeon-6335-uctl";
reg = <0x11800 0x6f000000 0x00 0x100>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
refclk-frequency = <0xb71b00>;
refclk-type = "crystal";
ehci@16f0000000000 {
compatible = "cavium,octeon-6335-ehci", "usb-ehci";
reg = <0x16f00 0x00 0x00 0x100>;
interrupts = <0x00 0x38>;
big-endian-regs;
};
ohci@16f0000000400 {
compatible = "cavium,octeon-6335-ohci", "usb-ohci";
reg = <0x16f00 0x400 0x00 0x100>;
interrupts = <0x00 0x38>;
big-endian-regs;
};
};
};
};
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