blob: 357cc1e4194e9b9de94ee1e50e08f66eda7c49e8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 16 May 2021 14:05:17 -0500
Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,8 @@ properties:
- sifive,u5
- sifive,u7
- canaan,k210
+ - thead,c906
+ - thead,c910
- const: riscv
- items:
- enum:
|