1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
From 5e339e1502c9be0f624398cf774e5880a6d1a677 Mon Sep 17 00:00:00 2001
From: Lee Jackson <lee.jackson@arducam.com>
Date: Wed, 10 Jan 2024 09:06:16 +0800
Subject: [PATCH] drivers: media: arducam_64mp: Add V4L2_CID_LINK_FREQ control
Add V4L2_CID_LINK_FREQ as a read-only control with a value of 456 Mhz.
This will be used by the CFE driver to corretly setup the DPHY timing
parameters in the CSI-2 block.
Signed-off-by: Lee Jackson <lee.jackson@arducam.com>
---
drivers/media/i2c/arducam_64mp.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/drivers/media/i2c/arducam_64mp.c
+++ b/drivers/media/i2c/arducam_64mp.c
@@ -143,6 +143,10 @@ struct arducam_64mp_mode {
struct arducam_64mp_reg_list reg_list;
};
+static const s64 arducam_64mp_link_freq_menu[] = {
+ ARDUCAM_64MP_DEFAULT_LINK_FREQ,
+};
+
static const struct arducam_64mp_reg mode_common_regs[] = {
{0x0100, 0x00},
{0x0136, 0x18},
@@ -2272,9 +2276,11 @@ static int arducam_64mp_init_controls(st
struct v4l2_ctrl_handler *ctrl_hdlr;
struct i2c_client *client = v4l2_get_subdevdata(&arducam_64mp->sd);
struct v4l2_fwnode_device_properties props;
+ struct v4l2_ctrl *link_freq;
unsigned int i;
int ret;
u8 test_pattern_max;
+ u8 link_freq_max;
ctrl_hdlr = &arducam_64mp->ctrl_handler;
ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);
@@ -2292,6 +2298,16 @@ static int arducam_64mp_init_controls(st
ARDUCAM_64MP_PIXEL_RATE, 1,
ARDUCAM_64MP_PIXEL_RATE);
+ /* LINK_FREQ is also read only */
+ link_freq_max = ARRAY_SIZE(arducam_64mp_link_freq_menu) - 1;
+ link_freq =
+ v4l2_ctrl_new_int_menu(ctrl_hdlr, &arducam_64mp_ctrl_ops,
+ V4L2_CID_LINK_FREQ,
+ link_freq_max, 0,
+ arducam_64mp_link_freq_menu);
+ if (link_freq)
+ link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
/*
* Create the controls here, but mode specific limits are setup
* in the arducam_64mp_set_framing_limits() call below.
|