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From db90a5e5fc2fbd843b29eb8110ed5e03604a2887 Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Wed, 20 Sep 2023 13:04:54 +0100
Subject: [PATCH] arm: dt: add dtparams for PCIe reset timing override
The Pi 5 variant gets two parameters so that the CM4-compatible
name will also work on Pi 5.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
---
arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 ++
arch/arm/boot/dts/bcm2712-rpi-5-b.dts | 2 ++
arch/arm/boot/dts/overlays/README | 7 +++++++
3 files changed, 11 insertions(+)
--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
@@ -446,5 +446,7 @@ i2c_csi_dsi0: &i2c0 {
cam1_reg = <&cam1_reg>,"status";
cam1_reg_gpio = <&cam1_reg>,"gpio:4",
<&cam1_reg>,"gpio:0=", <&gpio>;
+
+ pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0";
};
};
--- a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
+++ b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
@@ -814,6 +814,8 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
pciex1 = <&pciex1>, "status";
pciex1_gen = <&pciex1> , "max-link-speed:0";
pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?";
+ pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
+ pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
random = <&random>, "status";
rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0";
spi = <&spi0>, "status";
--- a/arch/arm/boot/dts/overlays/README
+++ b/arch/arm/boot/dts/overlays/README
@@ -280,6 +280,10 @@ Params:
(2711 only, but not applicable on CM4S)
N.B. USB-A ports on 4B are subsequently disabled
+ pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock
+ activation and PERST# deassertion
+ (CM4 and 2712, default "0")
+
pciex1 Set to "on" to enable the external PCIe link
(2712 only, default "off")
@@ -290,6 +294,9 @@ Params:
PCIe link for devices that have broken
implementations (2712 only, default "off")
+ pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms
+ (2712 only, default "0")
+
spi Set to "on" to enable the spi interfaces
(default "off")
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