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From 72bfb10c9393688d00e4e0b00d416e23c2753318 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 17 Feb 2023 15:07:29 +0100
Subject: [PATCH] drm/vc4: hvs: Use switch statement to simplify
enabling/disabling irq
Since we'll support BCM2712 soon, let's move the logic to enable and
disable the end-of-frame interrupts to a switch to extend it more
easily.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_hvs.c | 42 ++++++++++++++++++++++++++---------
1 file changed, 32 insertions(+), 10 deletions(-)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -416,24 +416,46 @@ static void vc4_hvs_irq_enable_eof(const
unsigned int channel)
{
struct vc4_dev *vc4 = hvs->vc4;
- u32 irq_mask = vc4->gen == VC4_GEN_5 ?
- SCALER5_DISPCTRL_DSPEIEOF(channel) :
- SCALER_DISPCTRL_DSPEIEOF(channel);
- HVS_WRITE(SCALER_DISPCTRL,
- HVS_READ(SCALER_DISPCTRL) | irq_mask);
+ switch (vc4->gen) {
+ case VC4_GEN_4:
+ HVS_WRITE(SCALER_DISPCTRL,
+ HVS_READ(SCALER_DISPCTRL) |
+ SCALER_DISPCTRL_DSPEIEOF(channel));
+ break;
+
+ case VC4_GEN_5:
+ HVS_WRITE(SCALER_DISPCTRL,
+ HVS_READ(SCALER_DISPCTRL) |
+ SCALER5_DISPCTRL_DSPEIEOF(channel));
+ break;
+
+ default:
+ break;
+ }
}
static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
unsigned int channel)
{
struct vc4_dev *vc4 = hvs->vc4;
- u32 irq_mask = vc4->gen == VC4_GEN_5 ?
- SCALER5_DISPCTRL_DSPEIEOF(channel) :
- SCALER_DISPCTRL_DSPEIEOF(channel);
- HVS_WRITE(SCALER_DISPCTRL,
- HVS_READ(SCALER_DISPCTRL) & ~irq_mask);
+ switch (vc4->gen) {
+ case VC4_GEN_4:
+ HVS_WRITE(SCALER_DISPCTRL,
+ HVS_READ(SCALER_DISPCTRL) &
+ ~SCALER_DISPCTRL_DSPEIEOF(channel));
+ break;
+
+ case VC4_GEN_5:
+ HVS_WRITE(SCALER_DISPCTRL,
+ HVS_READ(SCALER_DISPCTRL) &
+ ~SCALER5_DISPCTRL_DSPEIEOF(channel));
+ break;
+
+ default:
+ break;
+ }
}
static struct vc4_hvs_dlist_allocation *
|