starfive: add new target for StarFive JH7100/7110 SoC

This target adds support for the StarFive JH7100 and JH7110 SoCs, based on
6.1, as well as a couple boards equipped with these.

Specifications:

SoCs:

JH7100:
 - StarFive JH7100 dual-core RISC-V (U74, RC64GC)
 - additional monitoring (S7) and control (E24) cores
 - 2Mb L2 cache

JH7110:
 - StarFive JH7110 quad-core RISC-V (U74, RV64GC)
 - additional monitoring (S7) and control (E24) cores
 - 2Mb L2 cache

Boards:

VisionFive1:
 - JH7100 @ 1GHz
 - Memory: 8Gb LPDDR4
 - 4x USB3.0
 - 1x GBit ethernet
 - AMPak 6236 wifi / bluetooth
 - audio
 - powered via USB-C

VisionFive2:
 - JH7110 @ 1.5GHz
 - Memory: 2/4/8Gb DDR4
 - 2x Gbit ethernet
 - 2x USB3.0 / 2x USB2.0
 - eMMC / SDIO
 - various multimedia input/outputs (MIPI CSI, HDMI, audio)
 - M.2 key M slot
 - PoE support
 - powered via USB-C

Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

1 files changed, 129 insertions, 0 deletions

diff --git a/target/linux/starfive/patches-6.1/0078-media-cadence-Add-operation-on-reset.patch b/target/linux/starfive/patches-6.1/0078-media-cadence-Add-operation-on-reset.patch
new file mode 100644
index 0000000000..2cc7b69089
--- /dev/null
+++ b/target/linux/starfive/patches-6.1/0078-media-cadence-Add-operation-on-reset.patch
@@ -0,0 +1,129 @@
+From 2fbf4d367b25de4fa2f2d9cec57c88766c37d9de Mon Sep 17 00:00:00 2001
+From: Jack Zhu <jack.zhu@starfivetech.com>
+Date: Tue, 23 May 2023 16:56:24 +0800
+Subject: [PATCH 078/122] media: cadence: Add operation on reset
+
+Add operation on reset for Cadence MIPI-CSI2 RX Controller.
+
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
+---
+ drivers/media/platform/cadence/cdns-csi2rx.c | 40 +++++++++++++++++---
+ 1 file changed, 35 insertions(+), 5 deletions(-)
+
+--- a/drivers/media/platform/cadence/cdns-csi2rx.c
++++ b/drivers/media/platform/cadence/cdns-csi2rx.c
+@@ -13,6 +13,7 @@
+ #include <linux/of_graph.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/reset.h>
+ #include <linux/slab.h>
+ 
+ #include <media/v4l2-ctrls.h>
+@@ -68,6 +69,9 @@ struct csi2rx_priv {
+ 	struct clk			*sys_clk;
+ 	struct clk			*p_clk;
+ 	struct clk			*pixel_clk[CSI2RX_STREAMS_MAX];
++	struct reset_control		*sys_rst;
++	struct reset_control		*p_rst;
++	struct reset_control		*pixel_rst[CSI2RX_STREAMS_MAX];
+ 	struct phy			*dphy;
+ 
+ 	u8				lanes[CSI2RX_LANES_MAX];
+@@ -112,6 +116,7 @@ static int csi2rx_start(struct csi2rx_pr
+ 	if (ret)
+ 		return ret;
+ 
++	reset_control_deassert(csi2rx->p_rst);
+ 	csi2rx_reset(csi2rx);
+ 
+ 	reg = csi2rx->num_lanes << 8;
+@@ -154,6 +159,8 @@ static int csi2rx_start(struct csi2rx_pr
+ 		if (ret)
+ 			goto err_disable_pixclk;
+ 
++		reset_control_deassert(csi2rx->pixel_rst[i]);
++
+ 		writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
+ 		       csi2rx->base + CSI2RX_STREAM_CFG_REG(i));
+ 
+@@ -169,13 +176,16 @@ static int csi2rx_start(struct csi2rx_pr
+ 	if (ret)
+ 		goto err_disable_pixclk;
+ 
++	reset_control_deassert(csi2rx->sys_rst);
+ 	clk_disable_unprepare(csi2rx->p_clk);
+ 
+ 	return 0;
+ 
+ err_disable_pixclk:
+-	for (; i > 0; i--)
++	for (; i > 0; i--) {
++		reset_control_assert(csi2rx->pixel_rst[i - 1]);
+ 		clk_disable_unprepare(csi2rx->pixel_clk[i - 1]);
++	}
+ 
+ err_disable_pclk:
+ 	clk_disable_unprepare(csi2rx->p_clk);
+@@ -188,14 +198,17 @@ static void csi2rx_stop(struct csi2rx_pr
+ 	unsigned int i;
+ 
+ 	clk_prepare_enable(csi2rx->p_clk);
++	reset_control_assert(csi2rx->sys_rst);
+ 	clk_disable_unprepare(csi2rx->sys_clk);
+ 
+ 	for (i = 0; i < csi2rx->max_streams; i++) {
+ 		writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
+ 
++		reset_control_assert(csi2rx->pixel_rst[i]);
+ 		clk_disable_unprepare(csi2rx->pixel_clk[i]);
+ 	}
+ 
++	reset_control_assert(csi2rx->p_rst);
+ 	clk_disable_unprepare(csi2rx->p_clk);
+ 
+ 	if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))
+@@ -299,6 +312,16 @@ static int csi2rx_get_resources(struct c
+ 		return PTR_ERR(csi2rx->p_clk);
+ 	}
+ 
++	csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
++								    "sys");
++	if (IS_ERR(csi2rx->sys_rst))
++		return PTR_ERR(csi2rx->sys_rst);
++
++	csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
++								  "reg_bank");
++	if (IS_ERR(csi2rx->p_rst))
++		return PTR_ERR(csi2rx->p_rst);
++
+ 	csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy");
+ 	if (IS_ERR(csi2rx->dphy)) {
+ 		dev_err(&pdev->dev, "Couldn't get external D-PHY\n");
+@@ -349,14 +372,21 @@ static int csi2rx_get_resources(struct c
+ 	}
+ 
+ 	for (i = 0; i < csi2rx->max_streams; i++) {
+-		char clk_name[16];
++		char name[16];
+ 
+-		snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i);
+-		csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name);
++		snprintf(name, sizeof(name), "pixel_if%u_clk", i);
++		csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name);
+ 		if (IS_ERR(csi2rx->pixel_clk[i])) {
+-			dev_err(&pdev->dev, "Couldn't get clock %s\n", clk_name);
++			dev_err(&pdev->dev, "Couldn't get clock %s\n", name);
+ 			return PTR_ERR(csi2rx->pixel_clk[i]);
+ 		}
++
++		snprintf(name, sizeof(name), "pixel_if%u", i);
++		csi2rx->pixel_rst[i] =
++			devm_reset_control_get_optional_exclusive(&pdev->dev,
++								  name);
++		if (IS_ERR(csi2rx->pixel_rst[i]))
++			return PTR_ERR(csi2rx->pixel_rst[i]);
+ 	}
+ 
+ 	return 0;