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authorOlliver Schinagl <oliver@schinagl.nl>2022-08-30 21:25:25 +0200
committerSander Vanheule <sander@svanheule.net>2022-12-27 16:31:48 +0100
commit758c88b969639d0e6b684669d2e54dd1be3102f4 (patch)
treee7d26b19583851656d58903b8552daa4d4fe2077 /target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c
parent2c40359c5c12621fa386efca3139ea523db6d39f (diff)
realtek: Whitespace and codestyle cleanup
Fix some ugly whitepsaces and codestyle issues around the realtek sources. While this is by no means perfect, it catches what it caught. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Diffstat (limited to 'target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c')
1 files changed, 25 insertions, 25 deletions
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c
index 2fc8d37f3e..8a2621fb28 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/qos.c
@@ -2,8 +2,8 @@
#include <net/dsa.h>
#include <linux/delay.h>
-
#include <asm/mach-rtl838x/mach-rtl83xx.h>
+
#include "rtl83xx.h"
static struct rtl838x_switch_priv *switch_priv;
@@ -20,28 +20,28 @@ int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7};
static void rtl839x_read_scheduling_table(int port)
{
- u32 cmd = 1 << 9 /* Execute cmd */
- | 0 << 8 /* Read */
- | 0 << 6 /* Table type 0b00 */
- | (port & 0x3f);
+ u32 cmd = 1 << 9 | /* Execute cmd */
+ 0 << 8 | /* Read */
+ 0 << 6 | /* Table type 0b00 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
static void rtl839x_write_scheduling_table(int port)
{
- u32 cmd = 1 << 9 /* Execute cmd */
- | 1 << 8 /* Write */
- | 0 << 6 /* Table type 0b00 */
- | (port & 0x3f);
+ u32 cmd = 1 << 9 | /* Execute cmd */
+ 1 << 8 | /* Write */
+ 0 << 6 | /* Table type 0b00 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
static void rtl839x_read_out_q_table(int port)
{
- u32 cmd = 1 << 9 /* Execute cmd */
- | 0 << 8 /* Read */
- | 2 << 6 /* Table type 0b10 */
- | (port & 0x3f);
+ u32 cmd = 1 << 9 | /* Execute cmd */
+ 0 << 8 | /* Read */
+ 2 << 6 | /* Table type 0b10 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
@@ -56,12 +56,10 @@ static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, boo
u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
{
- u32 rate;
-
if (port > priv->cpu_port)
return 0;
- rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff;
- return rate;
+
+ return sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff;
}
/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */
@@ -86,8 +84,10 @@ void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
{
if (port > priv->cpu_port)
return;
+
if (queue > 7)
return;
+
sw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue));
}
@@ -118,7 +118,8 @@ static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv)
sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
/* Enable storm control on all ports with a PHY and limit rates,
- * for UC and MC for both known and unknown addresses */
+ * for UC and MC for both known and unknown addresses
+ */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy) {
sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
@@ -180,7 +181,7 @@ int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate
sw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8));
rtl839x_write_scheduling_table(port);
-
+
mutex_unlock(&priv->reg_mutex);
return old_rate;
@@ -317,7 +318,7 @@ void rtl839x_setup_prio2queue_matrix(int *min_queues)
/* Sets the CPU queue depending on the internal priority of a packet */
void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)
{
- int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP
+ int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP
: RTL839X_QM_PKT2CPU_INTPRI_MAP;
int i;
u32 v;
@@ -351,7 +352,6 @@ void rtl83xx_set_ingress_priority(int port, int priority)
sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port));
else
sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port));
-
}
int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)
@@ -367,6 +367,7 @@ int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)
if (v & BIT(19))
return WEIGHTED_ROUND_ROBIN;
+
return WEIGHTED_FAIR_QUEUE;
}
@@ -386,7 +387,7 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port
// Get current OAM state
oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port));
-
+
// Disable OAM to block traffice
v = sw_r32(RTL839X_OAM_CTRL);
sw_w32_mask(0, 1, RTL839X_OAM_CTRL);
@@ -397,7 +398,7 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port
// Set port egress rate to unlimited
egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF);
-
+
// Wait until the egress used page count of that port is 0
i = 0;
do {
@@ -528,7 +529,7 @@ void rtl839x_config_qos(void)
for (p = 0; p < 8; p++)
v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3);
sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP);
-
+
/* Configure Drop Precedence for Drop Eligible Indicator (DEI)
* Index 0: 0
* Index 1: 2
@@ -572,5 +573,4 @@ void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv)
rtl838x_rate_control_init(priv);
else if (priv->family_id == RTL8390_FAMILY_ID)
rtl839x_rate_control_init(priv);
-
}
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