diff options
| author | Mirko Vogt <mirko-openwrt@nanl.de> | 2024-04-05 15:31:03 +0000 |
|---|---|---|
| committer | Sander Vanheule <sander@svanheule.net> | 2024-04-08 21:31:55 +0200 |
| commit | 0688cf5aebe1dc9a2e7f3820861783c2a7a75d44 (patch) | |
| tree | ca294c901f16aee197852594cf9bc7d0e3120ad6 /target/linux/realtek/dts-5.15 | |
| parent | 501ef81040baa2ee31de6dd9f75d619de0e4c9bc (diff) | |
realtek: add support for switch Zyxel GS1900-24EP
This device is very similar to the GS1900-24E switch (added in b515ad1),
except that the first 12 of 24 ethernet ports are capable of PoE and the
physical jacks are in the right order - unlike for the GS1900-24E, where
even and uneven ports are flipped (up <-> down on panel).
Zyxel version code for this device (-24EP) is: ABTO
Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
Diffstat (limited to 'target/linux/realtek/dts-5.15')
| -rw-r--r-- | target/linux/realtek/dts-5.15/rtl8382_zyxel_gs1900-24ep.dts | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/target/linux/realtek/dts-5.15/rtl8382_zyxel_gs1900-24ep.dts b/target/linux/realtek/dts-5.15/rtl8382_zyxel_gs1900-24ep.dts new file mode 100644 index 0000000000..8a77121f4c --- /dev/null +++ b/target/linux/realtek/dts-5.15/rtl8382_zyxel_gs1900-24ep.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rtl8380_zyxel_gs1900.dtsi" + +/ { + compatible = "zyxel,gs1900-24ep", "realtek,rtl838x-soc"; + model = "ZyXEL GS1900-24EP Switch"; +}; + +&uart1 { + status = "okay"; +}; + +&mdio { + EXTERNAL_PHY(0) + EXTERNAL_PHY(1) + EXTERNAL_PHY(2) + EXTERNAL_PHY(3) + EXTERNAL_PHY(4) + EXTERNAL_PHY(5) + EXTERNAL_PHY(6) + EXTERNAL_PHY(7) + + EXTERNAL_PHY(16) + EXTERNAL_PHY(17) + EXTERNAL_PHY(18) + EXTERNAL_PHY(19) + EXTERNAL_PHY(20) + EXTERNAL_PHY(21) + EXTERNAL_PHY(22) + EXTERNAL_PHY(23) +}; + +&switch0 { + ports { + SWITCH_PORT(0, 1, qsgmii) + SWITCH_PORT(1, 2, qsgmii) + SWITCH_PORT(2, 3, qsgmii) + SWITCH_PORT(3, 4, qsgmii) + SWITCH_PORT(4, 5, qsgmii) + SWITCH_PORT(5, 6, qsgmii) + SWITCH_PORT(6, 7, qsgmii) + SWITCH_PORT(7, 8, qsgmii) + + SWITCH_PORT(8, 9, internal) + SWITCH_PORT(9, 10, internal) + SWITCH_PORT(10, 11, internal) + SWITCH_PORT(11, 12, internal) + SWITCH_PORT(12, 13, internal) + SWITCH_PORT(13, 14, internal) + SWITCH_PORT(14, 15, internal) + SWITCH_PORT(15, 16, internal) + + SWITCH_PORT(16, 17, qsgmii) + SWITCH_PORT(17, 18, qsgmii) + SWITCH_PORT(18, 19, qsgmii) + SWITCH_PORT(19, 20, qsgmii) + SWITCH_PORT(20, 21, qsgmii) + SWITCH_PORT(21, 22, qsgmii) + SWITCH_PORT(22, 23, qsgmii) + SWITCH_PORT(23, 24, qsgmii) + }; +}; |