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authorJohn Crispin <john@openwrt.org>2012-07-24 20:37:50 +0000
committerJohn Crispin <john@openwrt.org>2012-07-24 20:37:50 +0000
commit6641024f50b61178a07fc2ac846fb0ce8f53ee6f (patch)
treef35c82aaf0aa49b6ea6b4dc78cc39d764a280a40 /target/linux/ramips
parentcb0eccf529fa7c7410997e88f5add533419ba76d (diff)
uart_clk on Rt3352F is always 40MHz
Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock. Signed-off-by: Daniel Golle <dgolle@allnet.de> SVN-Revision: 32812
Diffstat (limited to 'target/linux/ramips')
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 4a99cf39e2..958547611b 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+ rt305x_uart_clk.rate = 40000000;
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
} else {
BUG();
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