blob: eea7cf491163136cd8b76868cb6e4bc79bda4604 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
/////////////////////////////////////////////////////////////////////////////////
// Copyright (c) Electronic Arts Inc. All rights reserved.
/////////////////////////////////////////////////////////////////////////////////
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H
#define EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
#pragma once
#endif
/////////////////////////////////////////////////////////////////////////////////
//
// void EASTL_ARCH_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
//
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_8)
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8)
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8)
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_16)
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16)
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16)
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_32)
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32)
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32)
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32)
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_64)
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64)
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64)
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64)
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_128)
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128)
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 0
#endif
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128)
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 1
#else
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 0
#endif
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H */
|