From aaabd3cf8c041b5122ca252f51fa616833e18749 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 11 Aug 2022 00:54:01 -0500
Subject: [PATCH 078/117] riscv: dts: allwinner: Add SPI support
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
.../dts/allwinner/sun20i-d1-lichee-rv.dts | 6 +++
.../boot/dts/allwinner/sun20i-d1-nezha.dts | 44 ++++++++++++++++
arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 51 +++++++++++++++++++
3 files changed, 101 insertions(+)
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
@@ -65,6 +65,12 @@
status = "okay";
};
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
pinctrl-names = "default";
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
@@ -19,6 +19,7 @@
ethernet1 = &xr829;
mmc0 = &mmc0;
serial0 = &uart0;
+ spi0 = &spi0;
};
chosen {
@@ -157,6 +158,49 @@
pinctrl-names = "default";
status = "okay";
};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot0";
+ reg = <0x00000000 0x00100000>;
+ };
+
+ partition@100000 {
+ label = "uboot";
+ reg = <0x00100000 0x00300000>;
+ };
+
+ partition@400000 {
+ label = "secure_storage";
+ reg = <0x00400000 0x00100000>;
+ };
+
+ partition@500000 {
+ label = "sys";
+ reg = <0x00500000 0x0fb00000>;
+ };
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
@@ -179,6 +179,24 @@
};
/omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pb_pins: spi1-pb-pins {
+ pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_pd_pins: spi1-pd-pins {
+ pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
uart0_pb8_pins: uart0-pb8-pins {
pins = "PB8", "PB9";
function = "uart0";
@@ -631,6 +649,39 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ };
+
+ spi0: spi@4025000 {
+ compatible = "allwinner,sun20i-d1-spi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x4025000 0x1000>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ num-cs = <1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@4026000 {
+ compatible = "allwinner,sun20i-d1-spi-dbi",
+ "allwinner,sun50i-r329-spi-dbi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x4026000 0x1000>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ num-cs = <1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
usb_otg: usb@4100000 {