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* kernel: bump 5.15 to 5.15.117John Audia2023-06-16
| | | | | | | | | | | | | | | | Manually rebased: generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch Removed upstreamed: generic/backport-5.15/830-v6.2-ata-ahci-fix-enum-constants-for-gcc-13.patch All other patches automatically rebased. Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3 Run-tested: ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me>
* kernel: Set CONFIG_FRAME_WARN depending on targetHauke Mehrtens2023-06-02
| | | | | | | | This set the CONFIG_FRAME_WARN option depending on some target settings. It will use the default from the upstream kernel and not the hard coded value of 1024 now. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* sifiveu: add new target for SiFive U-based boardsZoltan HERPAI2023-05-28
RISC-V is a new CPU architecture aimed to be fully free and open. This target will add support for it, based on 5.15. Supports running on: - HiFive Unleashed - FU540, first generation - HiFive Unmatched - FU740, current latest generation, PCIe SD-card images are generated, where the partitions are required to have specific type codes. As it is commonplace nowadays, OpenSBI is used as the first stage, with U-boot following as the proper bootloader. Specifications: HiFive Unleashed: - CPU: SiFive FU540 quad-core RISC-V (U54, RV64IMAFDC or RV64GC) - Memory: 8Gb - Ethernet: 1x 10/100/1000 - Console: via microUSB HiFive Unmatched: - CPU: SiFive FU740 quad-core RISC-V (U74, RV64IMAFDCB or RV64GCB) - Memory: 16Gb - Ethernet: 1x 10/100/1000 - USB: 4x USB 3.2 - PCIe: - 1x PCIe Gen3 x8 - 1x M.2 key M (PCIe x4) - 1x M.2 Key E (PCIe x1 / USB2.0) - Console: via microUSB Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>