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* realtek: do not reset SerDes on link changeBirger Koblitz2022-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not reset the RTL930x SerDes on link changes, instead set up the SDS with internal PHYs for the SFP+ ports only. This fixes the 8 1GBit ports on the Zyxel XGS1250 which do not work without this patch. A complete SerDes reset was performed on all SerDes links. For copper 1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There is however no support for setting up the XGMII link on RTL9300/RTL9310, thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit ports. No SerDes reset should be done for these links. The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely different. All these modes need to be suitably RX calibrated and the pre- main and post- amplifiers set up properly for TX. The 10GBit SFP+ fiber links are recalibrated instead of reset, which e.g. is necessary when someone pulls a module out and puts another in. This makes swapping out 10GBit fiber modules possible. 1GBit modules are not yet supported, nor any modules with an internal phy. Tested-by: Stijn Segers <foss@volatilesystems.org> Signed-off-by: Birger Koblitz <git@birger-koblitz.de> [rewrite commit message based on discussion] Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: Trap all frames with switch as destination to CPU-portBirger Koblitz2022-05-08
| | | | | | | | | | | | This fixes a bug where frames sent to the switch itself were flooded to all ports unless the MAC address of the CPU-port was learned otherwise. Tested-by: Wenli Looi <wlooi@ucalgary.ca> Tested-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Birger Koblitz <git@birger-koblitz.de> [fix code formatting] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix locking bug in rtl838x_hw_receive()Birger Koblitz2022-02-18
| | | | | | | | | | | | | | A Locking bug in the packet receive path was introduced with PR #4973. The following patch prevents the driver from locking after a few minutes with an endless flow of [ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8 [ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
* realtek: rtl83xx-phy: abstract and document PHY featuresDaniel Golle2022-02-17
| | | | | | | | | | | | | Replace magic values with more self-descriptive code now that I start to understand more about the design of the PHY (and MDIO controller). Remove one line before reading RTL8214FC internal PHY id which turned out to be a no-op and can hence safely be removed (confirmed by INAGAKI Hiroshi[1]) [1]: https://github.com/openwrt/openwrt/commit/df8e6be59a1fbce3f8c6878fe7440a129b1245d6#r66890713 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: fix locking issuesBirger Koblitz2022-02-17
| | | | | | | Fixe a coupld of locking issues found by applying lock debugging to the code. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: switch to use generic MDIO accessor functionsDaniel Golle2022-02-17
| | | | | | | | Instead of directly calling SoC-specific functions in order to access (paged) MII registers or MMD registers, create infrastructure to allow using the generic phy_*, phy_*_paged and phy_*_mmd functions. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: implement Clause-45 MDIO write on rtl931xDaniel Golle2022-02-17
| | | | | | | | | * Add missing Clause-45 write support for rtl931x * Switch to use helper functions in all Clause-45 access functions to make the code more readable. * More meaningful/unified debugging output (dynamic kprintf) Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: add support for port led configuration on RTL93XXBirger Koblitz2022-02-17
| | | | | | | | | Using the led-set attribute of a port in the dts we allow configuration of the port leds. Each led-set is being defined in the led-set configuration of the .dts, giving a specific configuration to steer the port LEDs via a serial connection. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for the RTL8221B PHYBirger Koblitz2022-02-17
| | | | | | | | | The RTL8221B PHY is a newer version of the RTL8226, also supporting 2.5GBit Ethernet. It is found with RTL931X devices such as the EdgeCore ECS4125-10P Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210Birger Koblitz2022-02-17
| | | | | | | | | | Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the Zyxel XGS1210 require special polling configuration settings in the RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them. Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits in the poll mask. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix link status detection on RTL9302 for SFP modulesBirger Koblitz2022-02-17
| | | | | | | For SFP slots on the RTL9302, the link status is not correctly detected. Use the link media status instead. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add RTL931X sub-targetBirger Koblitz2022-02-17
| | | | | | | | We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add HW support for RTL931X for PIE, L2 and STP agingBirger Koblitz2022-02-17
| | | | | | | | We add HW support routines for the RTL931X SoC family for handling the Packet Inspection Engine, L2 table handling and STP aging. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Store and Restore MC memberships for port enable/disableBirger Koblitz2022-02-17
| | | | | | | | | We need to store and restore MC memberships in HW when a port joins or leaves a bridge as well as when it is enabled or disabled, as these properties should not change in these situations. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Copy all BPDUs to the kernelBirger Koblitz2022-02-17
| | | | | | | | In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add L2 aging configuration functions for all SoC familiesBirger Koblitz2022-02-17
| | | | | | | | Instead of a generic L2 aging configuration function with complex logic, we implement an individual function for all SoC types. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realted: Add DSA bridge offload configurationBirger Koblitz2022-02-17
| | | | | | | | Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add Link Aggregation (aka trunking) supportBirger Koblitz2022-02-17
| | | | | | | | | This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filteringBirger Koblitz2022-02-17
| | | | | | | | Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SDS configuration routines for the RTL93XX platformsBirger Koblitz2022-02-17
| | | | | | | | Adds configuration routines for the internal SerDes of the RTL930X and RTL931X. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MAC config handling for all SoCsBirger Koblitz2022-02-17
| | | | | | | | | Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Allow PHY-IDs to differ from Port numbersBirger Koblitz2022-02-17
| | | | | | | | | We were using the PHY-ids (the reg entries in the PHY sections of the .dts) as the port numbers. Now scan the ports section in the .dts, and use the actual port numbers, following the phy-handle to the PHY properties. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Use SerDes Information from .dts for phylink configBirger Koblitz2022-02-17
| | | | | | | | When a port is brought up, read the SDS-id via the phy_device for a given port and use this to configure the SDS when it is brought up. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve IRQ request in Ethernet driverBirger Koblitz2022-02-17
| | | | | | | Improves the IRQ request code by using platform_get_irq() which provides better error handling. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X Ethernet driverBirger Koblitz2022-02-17
| | | | | | | | | | Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix Ethernet driver IRQ service routine for SMPBirger Koblitz2022-02-17
| | | | | | | Do not lock the register structure in IRQ context. It is not necessary and leads to lockups under SMP load. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: fix RTL839X receive tag decodingBirger Koblitz2022-02-17
| | | | | | Correct offset in RX tag structure. Correct offload decision flagging. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SerDes access functions for RTL931XBirger Koblitz2022-02-17
| | | | | | Adds RTL931X SerDes access functions as needed by the Ethernet driver. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X-specific Ethernet driver functionsBirger Koblitz2022-02-17
| | | | | | | Fix the update counter of the RX ring, add SDS access functions for RTL931X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: rename rtl838x_reg structureBirger Koblitz2022-02-17
| | | | | | | | Rename the SoC-specific rtl838x_reg structure in the Ethernet driver to avoid confusion with the structure of the same name in the DSA driver. New name is: rtl838x_eth_reg Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL839x TX CPU-TagBirger Koblitz2022-02-17
| | | | | | | | | | Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Increase zone size for Ethernet driver DMABirger Koblitz2022-02-17
| | | | | | | | | | Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger contiguous memory allocation for the DMA of the Ethernet driver. Increase the number of entries in the RX ring to 300 making use of the larger DMA region now possible for receiveing packets. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Create 4 different Realtek PlatformsBirger Koblitz2022-02-17
| | | | | | | | Creates RTL83XX as a basic kernel config parameter for the RTL838X, RTL839x, RTL930X and RTL931X platforms with respective configurations for the SoCs, which are introduced in addition. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: reset both ethernet NIC and queuesSander Vanheule2021-11-24
| | | | | | | | | | | | | | | Recent versions of Realtek's SDK reset both the ethernet NIC and queues (SW_NIC_RST and SW_Q_RST bits) when initialising the hardware. Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not supported by any current driver), the networking part of the SoC is not reset. This leads to unresponsive network after the restart. By resetting both the ethernet NIC and queues, networking always comes up reliably. Suggested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: re-enable IPv6 routingBjørn Mork2021-10-30
| | | | | | | | | | | | | | | | | | | | | | | Commit 03e1d93e0779 ("realtek: add driver support for routing offload") added routing offload for IPv4, but broke IPv6 routing completely. The routing table is empty and cannot be updated: root@gs1900-10hp:~# ip -6 route root@gs1900-10hp:~# ip -6 route add unreachable default RTNETLINK answers: Invalid argument As a side effect, this breaks opkg on IPv4 only systems too, since uclient-fetch fails when there are no IPv6 routes: root@gs1900-10hp:~# uclient-fetch http://192.168.99.1 Downloading 'http://192.168.99.1' Failed to send request: Operation not permitted Fix by returning NOTIFY_DONE when offloading is unsupported, falling back to default behaviour. Fixes: 03e1d93e0779 ("realtek: add driver support for routing offload") Signed-off-by: Bjørn Mork <bjorn@mork.no>
* realtek: Fix bug when accessing external PHYs on SoCs older than Revision CBirger Koblitz2021-10-09
| | | | | | | | | | RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address larger or equal to the CPU-port (52). This will make scanning the MDIO bus hang forever. Since the RTL8390 platform does not support more than 52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family of SoCs has a fixed mapping between port number and PHY-address. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: cleanup PHY driverBirger Koblitz2021-10-09
| | | | | | Removes unnecessary output from the RTL PHY drivers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add debugfs support for RTL9300Birger Koblitz2021-10-09
| | | | | | Adds support for debugfs on RTL9300, in particular the drop counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SoC-specific routing offload implementationBirger Koblitz2021-10-09
| | | | | | | | Adds SoC specific routing offload implementations for RTL8380/90 and RTL9300. RTL83xx supports merely nexthop routing, RTL9300 full host and prefix routes. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: add driver support for routing offloadBirger Koblitz2021-10-09
| | | | | | | | Add generic support for listening to FIB and Event notifier updates and use this information to hook into the L3 hardware capabilities of the RTL SoCs. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MDIO bus probing for RTL9300Birger Koblitz2021-10-09
| | | | | | | Improve handling of multi-gig ports on the RTL9300 when probing the MDIO bus. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix bug in VLAN ingress and egress filteringBirger Koblitz2021-10-09
| | | | | | | | | | | The ingress filter registers use 2 bits for each port to define the filtering state, whereas the egress filter uses 1 bit. So for for the ingress filter the register offset for a given port is: (port >> 4) << 4: since there are 16 entries in a register of 32 bits and for the egress filter: (port >> 5) << 4: since there are 32 entries in a register of 32 bits Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Configure initial L2 learning setupBirger Koblitz2021-10-09
| | | | | | | | Configure a sane L2 learning configuration upon DSA driver load so that the switch can start learning L2 addresses. Also configure the correct flood masks for broadcast and unknown unicast traffice. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add phylink configuration routines for RTL93xxBirger Koblitz2021-10-09
| | | | | | | | This adds RTL93xx-specific MAC configuration routines that allow also configuration of 10GBit links for phylink. There is support for the Realtek-specific HISGMI protocol. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL930x SoCsBirger Koblitz2021-10-09
| | | | | | Adds the RTL930x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL839x SoCsBirger Koblitz2021-10-09
| | | | | | Adds the RTL839x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL838x SoCsBirger Koblitz2021-10-09
| | | | | | Adds the RTL838x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add driver support for TC offloadingBirger Koblitz2021-10-09
| | | | | | | | This adds support for offloading TC flower by using the Packet Inspection Engine of the RTL-SoCs. Basic infrastructure support is provide with callbacks to the tc subsystem and support for HW packet counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add port to smi-bus address mappingBirger Koblitz2021-10-09
| | | | | | | | All RTL SoCs addresss PHYs via their port number, which is mapped to an SMI address. Add support for configuring this mapping via the .dts on all SoCs apart from the 839x, where the mapping to the 64 ports is fixed. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Increase maximum RX ring buffer lengthBirger Koblitz2021-10-09
| | | | | | | Increase the maximum ring buffer length in order to improve performance on RTL839x devices. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
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