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path: root/target/linux/ath79/dts/qca955x.dtsi
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* ath79: revert wmac node namesFelix Fietkau2025-07-09
| | | | | | | | | Changing the node names arbitrarily broke existing configurations, which rely on the device path in /etc/config/wireless. Revert that part of the change without altering the compatible strings. Fixes: 7e09959efda2 ("mac80211: fix wmac node names") Signed-off-by: Felix Fietkau <nbd@nbd.name>
* mac80211: fix wmac node namesRosen Penev2025-07-07
| | | | | | | | | | The upstream submission for this mandates the node to be named wifi instead of wmac. Change all ath79 entries to match the new names and remove the compatibility patch. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/19328 Signed-off-by: Robert Marko <robimarko@gmail.com>
* ath79: usb: remove reset namesRosen Penev2024-12-13
| | | | | | | | | Upstream uses devm_reset_control_array_get_optional_shared, which does not use names. reset-names is also not specified in the documentation. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/17118 Signed-off-by: John Crispin <john@phrozen.org>
* ath79: change phy-names to only usbRosen Penev2024-12-13
| | | | | | | | | Both generic-ehci.yaml and generic-ohci.yaml state that phy-names is to only be usb. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/17118 Signed-off-by: John Crispin <john@phrozen.org>
* ath79: usb: remove usb- from reset-namesRosen Penev2024-12-13
| | | | | | | | This matches the upstream PHY driver, which removed it. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/17118 Signed-off-by: John Crispin <john@phrozen.org>
* ath79: add missing usb-phy-analog reset to usb phys for QCA955xINAGAKI Hiroshi2024-10-19
| | | | | | | | | Add missing reset bits of USB phys on QCA955x SoCs to qca955x.dtsi to handle them. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Link: https://github.com/openwrt/openwrt/pull/16297 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* ath79: qca955x ag71xx upstream driver fixOskari Lemmela2024-09-22
| | | | | | | | Fix mdio probe in qca95xx devices and add mandatory clocks to dtsi Signed-off-by: Oskari Lemmela <oskari@lemmela.net> Link: https://github.com/openwrt/openwrt/pull/15926 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* ath79: add aliases to qca955x.dtsi for uart0/1INAGAKI Hiroshi2024-03-08
| | | | | | | | | | | | | | Add aliases with "serialN = &uartN;" of uart0/1 on QCA955x SoCs to qca955x.dtsi, to enable uart1 on Linux Kernel. without this: [ 0.342915] ar933x-uart 18500000.uart: unable to get alias id, err=-19 Additionally, remove "serial0 = &uart;" alias from QCA955x device dts/dtsi files. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ath79: add HighSpeed UART (uart1) support for QCA955xINAGAKI Hiroshi2024-03-08
| | | | | | | Add HighSpeed UART support to QCA955x series SoCs as a secondary UART (uart1). This UART is compatible with qca,ar9330-uart. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ath79: rename label of primary UART on QCA955x to "uart0"INAGAKI Hiroshi2024-03-08
| | | | | | | | Rename the DT label of the primary UART on Qualcomm Atheros QCA955x series SoCs to "uart0" from "uart" for the preparation to add HighSpeed UART (uart1) support. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ath79: fix avoid_unnecessary_addr_size warningsRosen Penev2024-01-05
| | | | | | Raised to dtc. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* ath79: rename pcie-controller to pcieRosen Penev2024-01-05
| | | | | | | pcie-controller was renamed to pcie since at least kernel 4.14. Match it here to get rid of dtc warnings. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* ath79: move usb led trigger node to SoC dtsiShiji Yang2022-11-12
| | | | | | | These frequently used usb led triggers are universal. They should be moved to SoC dtsi. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
* ath79: add missing clock name strings in SoC dtsiShiji Yang2022-11-09
| | | | | | | For all SoC in the ath79 target, the PLL controller provides 3 main clocks "cpu", "ddr" and "ahb" through the input clock "ref". Signed-off-by: Shiji Yang <yangshiji66@qq.com>
* ath79: qca955x: remove double declarationKoen Vandeputte2022-01-13
| | | | | | No need to mention the same value twice Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* ath79: fix various dts warningsChristian Lamparter2021-12-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ar9344_openmesh_mr600-v1.dts:40.10-44.5: Warning (gpios_property): /leds-ath9k/wifi2g: Missing property '#gpio-cells' in node /ahb/pcie-controller@180c0000/wifi@0,0 or bad phandle => added gpio-controller + #gpio-cells qca955x_zyxel_nbg6x16.dtsi:121.3-13: Warning (reg_format): /ahb/usb@1b000000/port@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) ../dts/qca955x_zyxel_nbg6x16.dtsi:131.3-13: Warning (reg_format): /ahb/usb@1b400000/port@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) qca955x_zyxel_nbg6x16.dtsi:120.20-123.4: Warning (avoid_default_addr_size): /ahb/usb@1b000000/port@1: Relying on default #address-cells value => ath79's usb-nodes are missing the address- and size-cells properties. These are needed for usb led trigger support. ar7242_ubnt_sw.dtsi:54.4-14: Warning (reg_format): /gpio_spi/gpio_spi@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) => the #address-cells and #size-cells had to be nudged. qca9531_dlink_dch-g020-a1.dts:19.6-39.4: Warning (i2c_bus_bridge): /i2c: incorrect #size-cells for I2C bus => #size-cells = <0>; Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ath79: enable UART in SoC DTSI filesAdrian Schmutzler2021-02-24
| | | | | | | | | | | | | | | The uart node is enabled on all devices except one (GL-USB150 *). Thus, let's not have a few hundred nodes to enable it, but do not disable it in the first place. Where the majority of devices is using it, also move the serial0 alias to the DTSI. *) Since GL-USB150 even defines serial0 alias, the missing uart is probably just a mistake. Anyway, disable it for now so this patch stays cosmetic. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: specify device-type for PCI controllersDavid Bauer2021-02-20
| | | | | | | | Specify the device_type property for PCI as well as PCIe controllers. Otherwise, the PCI range parser will not be selected when using kernel 5.10. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: move ath79-clk.h include to ath79.dtsiAdrian Schmutzler2020-09-25
| | | | | | | | | | ath79.dtsi uses ATH79_CLK_MDIO, so the include <dt-bindings/clock/ath79-clk.h> needs to be moved there. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: rearrange nand node by register addressSungbo Eo2020-07-02
| | | | | | | All other nodes in the DTS are placed in order of address space. Harmonize the nand nodes as well. Signed-off-by: Sungbo Eo <mans0n@gorani.run>
* ath79: drop and consolidate redundant chosen/bootargsAdrian Schmutzler2020-06-25
| | | | | | | | | | | | | | In ath79, for several SoCs the console bootargs are defined to the very same value in every device's DTS. Consolidate these definitions in the SoC dtsi files and drop further redundant definitions elsewhere. The only device without any bootargs set has been OpenMesh OM5P-AC V2. This will now inherit the setting from qca955x.dtsi Note that while this tidies up master a lot, it might develop into a frequent pitfall for backports. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: rename qca9557.dtsi to qca955x.dtsiDavid Bauer2020-04-24
There are at least 3 different chips in the Scorpion series of SoCs. Rename the common DTSI to better reflect it's purpose for the whole series. Also rename the compatible bindings from qca,ar9557 and qca,qca9557 to qca,qca9550. Signed-off-by: David Bauer <mail@david-bauer.net>
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